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參數(shù)資料
| 型號(hào)： | TDA9875AH/V2,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP |
| 文件頁(yè)數(shù)： | 65/96頁(yè) |
| 文件大小： | 324K |
| 代理商： | TDA9875AH/V2,557 |
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1999 Dec 20
68
Philips Semiconductors
Product specication
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER
Table 69 Subaddress 36 (note 1)
Note
1. The default setting at power-up is 0000 0000.
Table 70 System clock frequency selection
Note
1. With 16.384 MHz the duty cycle is 33%.
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
0
default value
6
B6
0
default value
5
B5
0
default value
4
SYSCL1
system clock frequency selection (see Table 70)
3
SYSCL0
2
SYSOUT
1
enables the output of a system (or master) clock signal at pin SYSCLK
0
the output will be off, thereby improving the EMC performance
1I2SFORM
1
an MSB-aligned (MSB-rst) serial output format is selected, i.e. a level change at
pin WS indicates the beginning of a new audio sample
0
the standard I2S-bus output format is selected
0 (LSB)
I2SOUT
1
enables the I2S-bus outputs (both serial data outputs plus serial bit clock and word
select) in a format determined by bit I2SFORM; the TDA9875A is then an I2S-bus
master
0
the outputs mentioned will be 3-stated, thereby improving the EMC performance
B4
B3
SYSCLK OUTPUT
FREQUENCY (MHz)
0
256fs
8.192
0
1
384fs
12.288
1
0
512fs
16.384(1)
1
768fs
24.576
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