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參數(shù)資料
| 型號： | TDA9875AH/V2,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP |
| 文件頁數(shù)： | 28/96頁 |
| 文件大?。?/td> | 324K |
| 代理商： | TDA9875AH/V2,557 |
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1999 Dec 20
34
Philips Semiconductors
Product specication
Digital TV Sound Processor (DTVSP)
TDA9875A
The following sub-sections provide a detailed description of the slave receiver registers.
10.3.1
AGC GAIN REGISTER
If the automatic gain control function is switched off in the general configuration register, the contents of this register will
define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF
ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control
function, the latest gain control setting is copied to the AGC gain register.
If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with
10 dB. The AGCLEV bit is also
active if the automatic gain function is enabled.
It should be noted that the input voltages should be considered as approximate target values.
Table 14 Subaddress 0 (note 1)
Note
1. The default setting at power-up is 0000 0000.
38
0
iiiii
I2S1 input level adjust
39
000ooooo
I2S1 output level adjust
40
0
mmm
0
s
I2S2 output select
41
0
iiiii
I2S2 input level adjust
42
000ooooo
I2S2 output level adjust
43
00000
f
beeper frequency
44
0
vvvvvv
beeper volume, Main and Auxiliary
45
bbbbbbbb
bass boost, Main left and right
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
B7
0
set to logic 0
6
B6
0
set to logic 0
5
AGCLEV
1
input signal scaled with
10 dB
0
input signal not scaled
4
AGCGAIN
gain control bits (see Table 15)
3
2
1
0 (LSB)
SUBADDRESS
(DECIMAL)
DATA
FUNCTION
MSB
LSB
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