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參數(shù)資料
| 型號： | TDA9875AH/V2,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP |
| 文件頁數(shù)： | 30/96頁 |
| 文件大小： | 324K |
| 代理商： | TDA9875AH/V2,557 |
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1999 Dec 20
36
Philips Semiconductors
Product specication
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.2
GENERAL CONFIGURATION REGISTER
Table 16 Subaddress 1 (note 1)
Note
1. The default setting at power-up is 1100 0000.
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
P2OUT
This bit controls the general purpose input/output pin P2. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reected
in the device status register (see Section 10.4.1).
6
P1OUT
This bit controls the general purpose input/output pin P1. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reected
in the device status register (see Section 10.4.1). P1OUT is recommended to be
used for switching an SIF trap for the adjacent picture carrier in designs that
employ such a trap.
5
STDBY
1
The IC is in the standby mode. Most functions are disabled and power dissipation
is somewhat reduced, but the analog selectors/matrices remain operational to
support analog copying from SCART-to-SCART.
0
The IC is in the normal operating mode. On return from standby mode, the device
is in its Power-on reset mode and needs to be re-initialized.
4
INIT
1
Causes initialization of the TDA9875A to its default settings. This has the same
effect as a Power-on reset. If there is a conict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.
0
Automatically reset to logic 0 after initialization. When set to logic 0, the
TDA9875A is in its normal operating mode.
3
CLRPOR
1
Resets the power fail detector to LOW.
0
This bit is automatically reset to logic 0 after bit POR in the device status register
has been reset.
2
AGCSLOW
1
A longer decay time is selected for input signals with strong video modulation
(intercarrier). This bit only has an effect when bit AGCOFF = 0.
0
Selects normal attack and decay times for the AGC.
1
AGCOFF
1
Forces the AGC block to a xed gain as dened in the AGC gain register.
0
The automatic gain control function is enabled and the contents of the AGC gain
register is ignored.
0 (LSB)
SIFSEL
1
Selects pin SIF2 for input (recommended for satellite tuner).
0
Selects pin SIF1 for input (terrestrial TV).
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