參數(shù)資料
型號(hào): TDA9874H
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 接收器
英文描述: Digital TV sound demodulator/decoder
中文描述: AM/FM, AUDIO DEMODULATOR, PQFP44
封裝: 14 X 14 MM, 2.20 MM HEIGHT, PLASTIC, SOT-205-1, QFP-44
文件頁(yè)數(shù): 32/56頁(yè)
文件大小: 254K
代理商: TDA9874H
1998 Apr 27
32
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874H
7.3.18
D
IGITAL
A
UDIO
I
NTERFACE
C
ONFIGURATION
R
EGISTER
(DAICONR)
The default setting at power-up is 00000000.
Table 47
Digital Audio Interface Configuration Register (subaddress 21)
Table 48
Description of DAICONR bits
Table 49
System clock frequency select
7
6
5
4
3
2
1
0
SYSCL1
SYSCL0
SYSOUT
I
2
SFORM
I
2
SOUT
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
SYSCL1
SYSCL0
SYSOUT
These 3 bits are not used and should be set to logic 0.
System clock frequency select.
These 2 bits select the frequency of the system clock;
see Table 49.
System clock output on/off.
SYSOUT = 1, enables the output of a system (or master)
clock signal at pin SYSCLK. SYSOUT = 0, the output will be off, thereby improving EMC
performance.
Serial output format.
I
2
SFORM = 1, selects an MSB-aligned, MSB-first output format,
i.e. a level change at the word select pin indicates the beginning of a new audio sample.
I
2
SFORM = 0, selects the standard I
2
S output format.
I
2
S output on/off.
I
2
SOUT = 1, enables the output of serial audio data (2 pins) plus
serial bit clock and word select in a format determined by the I
2
SFORM bit.
The TDA9874H then is an I
2
S-bus master. I
2
SOUT = 0, the outputs mentioned will be
3-stated, thereby improving EMC performance.
1
I
2
SFORM
0
I
2
SOUT
SYSCL1
SYSCL0
SYSCLK OUTPUT
FREQUENCY
(MHz)
0
0
1
1
0
1
0
1
256f
s
384f
s
512f
s
768f
s
8.192
12.288
16.384
24.576
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