參數(shù)資料
型號： TDA9874H
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： Digital TV sound demodulator/decoder
中文描述： AM/FM, AUDIO DEMODULATOR, PQFP44
封裝： 14 X 14 MM, 2.20 MM HEIGHT, PLASTIC, SOT-205-1, QFP-44
文件頁數(shù)： 20/56頁
文件大?。?/td> 254K
代理商： TDA9874H
1998 Apr 27
20
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874H
7.3.2
G
ENERAL
C
ONFIGURATION
R
EGISTER
(GCONR)
The default setting at power-up is 11000000.
Table 13
General Configuration Register (subaddress 1)
Table 14
Description of GCONR bits
7
6
5
4
3
2
1
0
P2OUT
P1OUT
STDBY
INIT
AGCSLOW
AGCOFF
SIFSEL
BIT
SYMBOL
DESCRIPTION
7
6
P2OUT
P1OUT
General purpose I/O pins 1 and 2.
These bits control general-purpose input/output
pins. The contents of these bits is written directly to the corresponding pins. If an input is
desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input
from the pins is reflected in the Device Status Register (see Section 7.4.1). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier in
designs that employ such a trap.
Standby mode on/off.
STDBY = 1, puts the TDA9874H into the Standby mode. Most
functions are disabled and power dissipation is somewhat reduced. STDBY = 0, the
TDA9874H is in its normal mode of operation. On return from Standby mode, the device
is in its Power-on reset mode and needs to be re-initialized with data defined by the
setmaker.
Initialize to default settings.
INIT = 1, causes initialization of TDA9874H to its default
settings. This has the same effect as a power-on reset. In case there is a conflict
between the default settings and any bit set HIGH in this register, the bits of this register
have priority over the corresponding default setting. This bit is automatically reset to
LOW after initialization has completed. When set LOW, the TDA9874H is in its normal
mode of operation.
This bit is not used and should be set to a logic 0.
AGC decay time.
AGCSLOW = 1, a longer decay time and larger hysteresis are
selected for input signals with strong video modulation (intercarrier). This bit has only an
effect, when bit AGCOFF = 0. AGCSLOW = 0, selects normal attack and decay times
for the AGC and a small hysteresis.
5
STDBY
4
INIT
3
2
AGCSLOW
Note.
AGCSLOW bit should be set to HIGH for best possible audio performance.
AGC on/off.
AGCOFF = 1, forces the AGC block to a fixed gain as defined in the
AGC Gain Register (see Section 7.3.1). AGCOFF = 0, the automatic gain control
function is enabled and the contents of the AGC gain register is ignored.
SIF input select.
SIFSEL = 1, selects pin SIF2 for input (recommended for satellite
tuner). SIFSEL = 0, pin SIF1 (recommended for terrestrial TV) is selected.
1
AGCOFF
0
SIFSEL
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