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參數(shù)資料
| 型號： | TDA9852H-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 39/40頁 |
| 文件大?。?/td> | 195K |
| 代理商： | TDA9852H-T |
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1997 Mar 11
8
Philips Semiconductors
Preliminary specication
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Fig.3 Pin configuration (SDIP-version).
handbook, halfpage
TDA9852
MHA310
1
2
42
41
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OUTL
LDL
VIL
EOL
CAV
Vref
LIL
AVL
SOL
LOL
CTW
CTS
CW
CS
VEO
VEI
CNR
CM
CDEC
GND
SDA
OUTR
LDR
VIR
EOR
CPS1
CPS2
LIR
AVR
SOR
LOR
CSS
CMO
CER
CADJ
CPH
CP2
CP1
VCAP
COMP
VCC
SCL
FUNCTIONAL DESCRIPTION
Stereo decoder
INPUT LEVEL ADJUSTMENT
The composite input signal is fed to the input level
adjustment stage. The control range is from
3.5 to +4.0 dB in steps of 0.5 dB. The subaddress
control 3 of Tables 5 and 6 and the level adjust setting of
Table 21 allows an optimum signal adjustment during the
set alignment. The maximum input signal voltage is
2 V (RMS).
STEREO DECODER
The output signal of the level adjustment stage is coupled
to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75
s fixed
de-emphasis filter and is fed into the dematrix circuit.
The decoded sub-signal L
R is sent to the stereo/SAP
switch. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
The stereo channel separation is adjusted by an automatic
procedure to be performed during set production. For a
detailed description see Section “Adjustment procedure”.
The stereo identification can be read by the I2C-bus
(see Table 2). Two different pilot thresholds
(data STS = 1; STS = 0) can be selected via the I2C-bus
(see Table 19).
SAP DEMODULATOR
The composite signal is fed from the output of the input
level adjustment stage to the SAP demodulator circuit
through a 5fH (fH = horizontal frequency) band-pass filter.
The demodulator level is automatically controlled.
The SAP demodulator includes internal noise and field
strength detectors that mute the SAP output in the event of
insufficient signal conditions. The SAP identification signal
can be read by the I2C-bus (see Table 2).
SWITCH
The stereo/SAP switch feeds either the L
R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/switching circuit. Table 12
shows the different switch modes provided at the output
pins LOR and LOL.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9853 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder and audio processor |
| TDA9853H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder and audio processor |
| TDA9853HV1 | 制造商:PHILIPS 功能描述:New |
| TDA9855 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9855/V2,112 | 功能描述:音頻放大器 BTSC STEREO DECODER RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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