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參數資料
| 型號： | TDA9852H-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 文件頁數： | 14/40頁 |
| 文件大?。?/td> | 195K |
| 代理商： | TDA9852H-T |
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1997 Mar 11
21
Philips Semiconductors
Preliminary specication
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
I2C-bus format to write (slave receives data)
Table 4
Explanation of I2C-bus format to write (slave receives data)
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5
Subaddress second byte after MAD
Note
1. In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1.
Table 6
Denition of third byte, third byte after MAD and SAD
S
SLAVE ADDRESS
R/W
A
SUBADDRESS
A
DATA
A
P
NAME
DESCRIPTION
S
START condition
Standard SLAVE ADDRESS (MAD)
101 101 1
R/W
0 (write)
A
acknowledge; generated by the slave
SUBADDRESS (SAD)
see Table 5
DATA
see Table 6
P
STOP condition
FUNCTION
REGISTER
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Volume right
VR
0
Volume left
VL
0
1
Control 1 (note 1)
CON1
0
1
0
1
Control 2
CON2
0
1
0
Control 3
CON3
0
1
Alignment 1
ALI1
0
1
0
Alignment 2
ALI2
0
1
0
1
Alignment 3
ALI3
0
1
0
1
0
FUNCTION
REGISTER
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Volume right
VR
0
VR6
VR5
VR4
VR3
VR2
VR1
VR0
Volume left
VL
0
VL6
VL5
VL4
VL3
VL2
VL1
VL0
Control 1
CON1
GMU
AVLON
LOFF
CCD
0
SC2
SC1
SC0
Control 2
CON2
SAP
STEREO
TZCM
1
LMU
EF2
EF1
EF0
Control 3
CON3
0
L3
L2
L1
L0
Alignment 1
ALI1
0
A14
A13
A12
A11
A10
Alignment 2
ALI2
STS
0
A24
A23
A22
A21
A20
Alignment 3
ALI3
ADJ
AT1
AT2
0
1
TC2
TC1
TC0
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相關代理商/技術參數 |
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| TDA9853 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder and audio processor |
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