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參數資料
| 型號： | TDA938X |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV signal processor-Teletext decoder with embedded m-Controller |
| 中文描述： | 電視信號處理器與嵌入式米圖文電視解碼器控制器 |
| 文件頁數： | 31/140頁 |
| 文件大?。?/td> | 570K |
| 代理商： | TDA938X |
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Philips Semiconductors
Preliminary specification
1999 Sep 28
31
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
Power-on Reset
An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDDP through a 10uF
capacitor, providing the VDD rise time does not exceed 1ms, and the oscillator start-up time does not exceed
10ms.
To ensure correct initialisation, the RESET pin must be held high long enough for the oscillator to settle following
power-up, usually a few milli-seconds. Once the oscillator is stable, a further 12 clocks are required to generate
the Reset (One machine cycle of the Micro-controller). Once the above reset condition has been detected an
internal reset signal is triggered which remains active for 2048 clock cycles.
Reduced Power modes
There are three power saving modes: Stand-by, Idle and Power Down. In all three modes the 3.3v power
supplies (Vddp, Vddc & Vdda) to the device must be maintained. Power saving is achieved by clock gating on
a section by section basis.
S
TAND
-
BY
M
ODE
When Stand-by mode is entered both Acquisition and Display sections are disabled. The following functions
remain active:-
80c51 Core
Memory Interface
I2C
Timer/Counters
WatchDog Timer
Software A/D
Pulse Width Modulators
To enter Stand-by mode, the STANDBY control bit in the ROMBANK SFR (Bit-7) must be set. It can be used in
conjunction with either Idle or Power-Down to switch between power saving modes. This mode enables the
80c51 core to decode either IR Remote Commands or receive IIC commands without the need to fully power
the device.
The Stand-by state is maintained upon exit from Idle / Power-Down. No wake-up from Stand-by is necessary
as the 80c51 core remains operational.
Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before
entering this mode.
I
DLE
M
ODE
During Idle mode, Acquisition, Display and the CPU sections of the device are disabled. The following functions
remain active:-
Memory Interface
I2C
Timer/Counters
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