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參數(shù)資料
| 型號(hào)： | TDA9330 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | I2C-bus controlled TV display processors |
| 中文描述： | 的I2C控制的電視顯示處理器總線 |
| 文件頁(yè)數(shù)： | 14/56頁(yè) |
| 文件大小： | 228K |
| 代理商： | TDA9330 |
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2000 May 08
14
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
Table 27
Long blanking mode
Table 28
Vertical free-running frequency in TV mode
Table 29
De-interlace phase
Table 30
Switch-off in vertical overscan
Table 31
Select vertical frequency
Table 32
Enable vertical guard (RGB blanking)
Table 33
Interlace
Table 34
Soft clipping level
Table 35
Clamp pulse timing
Note
1.
See Chapter “Characteristics”; note 13.
Table 36
Start line blanking (15 steps; 2 line locked clock
period per step; 1 line period is 440 LLC pulses)
Note
1.
See Chapter “Characteristics”; note 13.
Output status bits
Table 37
Power-on reset
Table 38
Field frequency indication
Table 39
Phase 1 (
1
) lock indication
LBM
BLANKING MODE
0
1
adapted to standard (50 or 60 Hz)
fixed in accordance with 50 Hz standard
VFF
FREQUENCY
0
1
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
DIP
PHASE
0
delay of 1st field (start of synchronized V
D
pulse coincides with H-flyback) with 0.5 H
delay of 2nd field with 0.5 H
1
OSO
MODE
0
1
switch-off undefined
switch-off in vertical overscan
SVF
MODE
0
1
vertical frequency is 50 or 60 Hz
vertical frequency is 100 or 120 Hz
EVG
VERTICAL GUARD MODE
0
1
not active
active
DL
STATUS
0
1
interlace
de-interlace
SC1
SC0
VOLTAGE DIFFERENCE
BETWEEN SOFT CLIPPING AND
PWL
0
0
1
1
0
1
0
1
0% above PWL
5% above PWL
10% above PWL
soft clipping off
HDCL
MODE
(1)
0
1
normal timing
HDTV timing
LBL3
LBL2
LBL1
LBL0
START LINE
BLANKING
(1)
0
0
1
0
1
1
0
1
1
0
1
1
+14 LLC
normal
16 LLC
POR
MODE
0
1
normal
power-down
FSI
FREQUENCY
0
1
50 or 100 Hz
60 or 120 Hz
SL
INDICATION
0
1
not locked
locked
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