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參數(shù)資料
| 型號(hào)： | TDA8798 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 8-bit, 100 Msps A/D converter with DPGA |
| 中文描述： | 雙8位，100 Msps的的A / D轉(zhuǎn)換器與DPGA |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 214K |
| 代理商： | TDA8798 |
1999 Sep 16
14
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
Note
1.
Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold
(1.65 V for nominal supply conditions), and should be correctly decoupled.
C
OMMON MODE REFERENCE OUTPUTS
(V
OREF
1
AND
V
OREF
2
)
V
o(ref)
reference output voltage
R
o(ref)
reference output resistance
I
o(ref)
reference maximum output
current
C
o(ref)
reference output capacitance
Serial Interface
V
DDA
0.42 V
400
170
V
μ
A
at V
o(cm)(ref)
at V
o(cm)(ref)
0.2 V
3
pF
D
IGITAL INPUTS
(SEN1, SEN2, SCLK, SDATA
AND
SMODE)
V
IL
V
IH
I
IH
I
IL
G
AIN CONTROL DATA TIMING
(see Fig.4)
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level input current
0
2.0
5
5
0
0
0.8
V
DDD
+5
+5
V
V
μ
A
μ
A
f
SCLK(max)
t
W(SCLKH)
t
W(SCLKL)
t
su(SEN-SCLK
)
t
h(SEN-SCLK)
t
su(SDATA-SCLK)
t
h(SMODE-SCLK)
SMODE to SCLK hold time
t
h(SMODE-SEN)
SMODE to SEN hold time
t
d(SEN-Q)
delay SEN rising edge to
change gain control register
value
t
d(SCLK-Q)
delay SCLK rising edge to
change gain control register
value
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
SEN to SCLK set-up time
SEN to SCLK hold time
SDATA to SCLK set-up time
5
20
20
5
5
5
5
5
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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