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參數(shù)資料
| 型號(hào)： | TDA8792 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3.3 V, 25 MHz 8-bit analog-to-digital converter ADC |
| 中文描述： | 3.3伏，25兆赫8位模擬數(shù)字轉(zhuǎn)換器模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 148K |
| 代理商： | TDA8792 |
1996 Feb 21
8
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the
device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant
attenuation.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
Output data acquisition: the output data is available after the maximum delay time of t
d
. In the event of 25 MHz clock
operation, the hardware design must be taken into account the t
d
and t
h
limits with respect to the input characteristics
of the acquisition circuit.
Maximum value standby mode start-up output delay time (HIGH-to-LOW transition):
2.
3.
4.
5.
6.
7.
.
E
FFECTIVE BITS
; see Figs 6 and 11; note 4
EB
effective bits
f
clk
= 25 MHz
f
i
= 2.0 MHz
f
i
= 4.43 MHz
f
i
= 7.5 MHz
f
i
= 10 MHz
7.4
7.3
7.2
7.0
bits
bits
bits
bits
D
IFFERENTIAL GAIN
; see note 5
G
diff
differential gain
f
clk
= 25 MHz;
PAL modulated ramp
1.5
%
D
IFFERENTIAL PHASE
; see note 5
diff
differential phase
f
clk
= 25 MHz;
PAL modulated ramp
0.5
deg
Timing (f
clk
= 25 MHz);
see Fig.3 and note 6
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
6
8
13
2
25
ns
ns
ns
3-state output delay times;
see Fig.4
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
17
22
20
22
28
30
28
30
ns
ns
ns
ns
Standby mode output delay times
t
dSTBLH
t
dSTBHL
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
200
note 7
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
100
clk
(MHz)
f
+
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