參數(shù)資料
型號: TDA8790
廠商: NXP Semiconductors N.V.
英文描述: 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter
中文描述: 8位,40 Msps的2.7至5.5 V通用模擬至數(shù)字轉(zhuǎn)換器
文件頁數(shù): 9/20頁
文件大?。?/td> 160K
代理商: TDA8790
1996 Feb 21
9
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
3.
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to
pins V
RB
and V
RT
via offset resistors R
OB
and R
OT
as shown in Fig.3.
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter,
to cover code 0 to code 255, is
b) Since R
L
, R
OB
and R
OT
have similar behaviour with respect to process and temperature variation, the ratio
R
R
OB
R
L
R
OT
+
+
will be kept reasonably constant from part to part. Consequently variation of the output codes
at a given input voltage depends mainly on the difference V
RT
V
RB
and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
4.
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC.
Output data acquisition: the output data is available after the maximum delay time of t
d
.
5.
6.
7.
8.
I
L
V
V
+
R
OB
R
L
R
OT
+
-----------------------------------------
=
V
i
R
L
I
L
×
R
R
L
R
OB
R
OT
+
+
-----------------------------------------
=
=
V
RT
V
RB
)
0.838
V
RT
V
RB
(
×
=
(
)
×
-----------------------------------------
Fig.3 Explanation of note 3.
handbook, halfpage
RLAD
ROT
VRT
VRM
VRB
ROB
code 255
code 0
7
6
9
MGD284
IL
RL
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