參數(shù)資料
型號: TDA8790
廠商: NXP Semiconductors N.V.
英文描述: 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter
中文描述: 8位,40 Msps的2.7至5.5 V通用模擬至數(shù)字轉(zhuǎn)換器
文件頁數(shù): 7/20頁
文件大?。?/td> 160K
代理商: TDA8790
1996 Feb 21
7
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
R
LAD
TC
RLAD
resistor ladder
temperature coefficient of the
resistor ladder
1.4
2.2
1860
4092
170
170
1.76
2.4
k
ppm
m
/K
mV
mV
V
V
osB
V
osT
V
i(p-p)
offset voltage BOTTOM
offset voltage TOP
analog input voltage (peak-to-peak
value)
note 2
note 2
note 3
Outputs
D
IGITAL OUTPUTS
D7
TO
D0 (
REFERENCED TO
V
SSD
)
V
OL
LOW level output voltage
V
OH
HIGH level output voltage
I
OZ
output current in 3-state mode
I
O
= 1 mA
I
O
=
1 mA
0.4 V < V
O
< V
DDO
0
V
DDO
0.5
20
0.5
V
DDO
+20
V
V
μ
A
Switching characteristics
C
LOCK INPUT
CLK; see Fig.4; note 1
f
clk(max)
t
CPH
t
CPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
40
9
9
MHz
ns
ns
Analog signal processing
L
INEARITY
INL
integral non-linearity
f
clk
= 40 MHz; ramp input;
see Fig.6
f
clk
= 40 MHz; ramp input;
see Fig.7
±
0.5
±
0.75
LSB
DNL
differential non-linearity
±
0.25
±
0.5
LSB
B
ANDWIDTH
(f
clk
= 40 MHz)
B
analog bandwidth
full-scale sine wave;
note 4
75% full-scale sine wave;
note 4
50% full-scale sine wave;
note 4
small signal at mid scale;
V
i
=
±
10 LSB at
code 128; note 4
10
MHz
13
MHz
20
MHz
350
MHz
I
NPUT SET RESPONSE
(f
clk
= 40 MHz; see Fig.8; note 5)
t
STLH
analog input settling time
LOW-to-HIGH
t
STHL
analog input settling time
HIGH-to-LOW
full-scale square wave
3
5
ns
full-scale square wave
3
5
ns
H
ARMONICS
; (f
clk
= 40 MH
Z
; see Fig.9; note 6)
THD
total harmonic distortion
f
i
= 4.43 MHz
50
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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