參數(shù)資料
型號(hào): TDA8790
廠商: NXP Semiconductors N.V.
英文描述: 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter
中文描述: 8位,40 Msps的2.7至5.5 V通用模擬至數(shù)字轉(zhuǎn)換器
文件頁數(shù): 8/20頁
文件大?。?/td> 160K
代理商: TDA8790
1996 Feb 21
8
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
Analog input voltages producing code 0 up to and including 256:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to 256 at T
amb
= 25
°
C.
2.
S
IGNAL
-
TO
-
NOISE RATIO
; see Fig.9; note 6
S/N
signal-to-noise ratio (full scale)
without harmonics;
f
clk
= 40 MHz;
f
i
= 4.43 MHz
47
dB
E
FFECTIVE BITS
; see Fig.9; note 6
EB
effective bits
f
clk
= 40 MHz
f
i
= 300 kHz
f
i
= 4.43 MHz
7.8
7.3
bits
bits
D
IFFERENTIAL GAIN
; see note 7
G
diff
differential gain
f
clk
= 40 MHz;
PAL modulated ramp
1.5
%
D
IFFERENTIAL PHASE
; see note 7
diff
differential phase
f
clk
= 40 MHz;
PAL modulated ramp
0.25
deg
Timing (f
clk
= 40 MHz; C
L
= 20 pF);
see Fig.4; note 8
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
8
8
8
12
17
18
5
15
20
21
ns
ns
ns
ns
ns
V
DDO
= 4.75 V
V
DDO
= 3.15 V
V
DDO
= 2.7 V
3-state sleep mode delay times;
see Fig.5
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
14
16
16
14
18
20
20
18
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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