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      參數(shù)資料
      型號: TDA8785
      廠商: NXP Semiconductors N.V.
      英文描述: 8-bit high-speed analog-to-digital converter with gain and offset controls
      中文描述: 8位高速模增益和偏移數(shù)字轉(zhuǎn)換器控制
      文件頁數(shù): 9/24頁
      文件大?。?/td> 169K
      代理商: TDA8785
      1997 Dec 18
      9
      Philips Semiconductors
      Product specification
      8-bit high-speed analog-to-digital converter
      with gain and offset controls
      TDA8785
      Slow offset amplifier inputs (pins V
      SOFF(p)
      and V
      SOFF(n)
      ) gain amplifier at 0 dB;
      note 1
      V
      offset(ADC)
      offset voltage at ADC input
      V
      SOFF(p)
      = 2 V;
      V
      SOFF(n)
      = 2.75 V
      V
      SOFF(p)
      = 2.75 V;
      V
      SOFF(n)
      = 2.75 V
      V
      SOFF(p)
      = 3.5 V;
      V
      SOFF(n)
      = 2.75 V
      0.25
      V
      0
      V
      0.25
      V
      I
      i
      Offset reference code; T
      amb
      = 25
      °
      C
      input current
      10
      μ
      A
      OFSRE
      OFSER
      offset reference (ADC output code)
      offset reference error on code 8
      V
      i(p)
      = V
      i(n)
      ;
      V
      FOFF(p)
      = V
      FOFF(n)
      ;
      V
      SOFF(p)
      = V
      SOFF(n)
      ;
      amplifier gain set at
      0 dB
      15
      8
      0
      +15
      code
      code
      Gain control inputs (pins V
      FSAD(p)
      and V
      FSAD(n)
      );
      see Fig.7
      G
      v(min)
      minimum voltage gain
      V
      FSAD(p)
      = 2 V;
      V
      FSAD(n)
      = 2.75 V
      V
      FSAD(p)
      = 3.5 V;
      V
      FSAD(n)
      = 2.75 V
      0
      dB
      G
      v(max)
      maximum voltage gain
      20
      dB
      I
      i
      DAC full-scale control inputs (pins V
      FSDAC(p)
      and V
      FSDAC(n)
      ) 150
      output load on pins V
      DACO(p)
      and V
      DACO(n)
      ;
      see Table 3
      input current
      10
      μ
      A
      V
      DACO(n)
      DAC negative output voltage (pin 8)
      code 0 at DAC inputs
      code 255 at DAC inputs;
      V
      FSDAC(p)
      = 2 V;
      V
      FSDAC(n)
      = 2.75 V
      code 255 at DAC inputs;
      V
      FSDAC(p)
      = 2.75 V;
      V
      FSDAC(n)
      = 2.75 V
      code 255 at DAC inputs;
      V
      FSDAC(p)
      = 3.5 V;
      V
      FSDAC(n)
      = 2.75 V
      V
      CCA
      V
      CCA
      0.4
      V
      V
      V
      CCA
      0.5
      V
      V
      CCA
      0.6
      V
      I
      i
      input current
      1
      μ
      A
      Bandwidth adjustment node input (pin B);
      see Fig.6
      Z
      i
      8-bit DAC; f
      clk
      = 30 MHz, ramp input; T
      amb
      = 25
      °
      C
      input impedance
      500
      Z
      o
      INL
      DNL
      output impedance
      integral non-linearity
      differential non-linearity
      150
      ±
      0.4
      ±
      0.4
      ±
      0.8
      ±
      1.0
      LSB
      LSB
      SYMBOL
      PARAMETER
      CONDITIONS
      MIN.
      TYP.
      MAX. UNIT
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