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參數(shù)資料
| 型號(hào)： | TDA8785 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit high-speed analog-to-digital converter with gain and offset controls |
| 中文描述： | 8位高速模增益和偏移數(shù)字轉(zhuǎn)換器控制 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 169K |
| 代理商： | TDA8785 |
1997 Dec 18
11
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
with gain and offset controls
TDA8785
Notes
1.
2.
V
os
is proportional to the amplifier gain. For instance, V
os
at 20 dB is the one indicated at 0 dB multiplied by 10.
It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.
Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; f
clk
= 30 MHz; no external
filtering on pin 6 (B).
The data set-up time (t
SU; DAT
) is the minimum period preceding the rising edge of the clock, that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (t
HD; DAT
) is the minimum period following the rising edge
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.
The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling
shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time t
X
.
3.
4.
5.
Timing
ADC
DIGITAL OUTPUTS
(C
L
= 15 pF)
t
ds
sampling delay time
t
h
output hold time
t
d
output delay time
DAC
OUTPUTS
(
PINS
V
DACO(p)
AND
V
DACO(n)
)
t
SU; DAT
data set-up time
t
HD; DAT
data hold time
t
S
DAC setting time (10 to 90%)
RSA
residual setting accuracy
7
1.5
16
ns
ns
ns
note 4
note 4
R
L
= 150
; C
L
= 15 pF
note 5; see Fig.8
0.3
8
0.1
2
2.5
ns
ns
ns
%
3-
STATE OUTPUT DELAY TIMES
(see Fig.5)
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
15
15
13
10
20
20
20
20
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
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