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參數(shù)資料
| 型號： | TDA8754HL/21 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LOW PROFILE, PLASTIC, SOT-486-1, MS-026, QFP-144 |
| 文件頁數(shù)： | 8/57頁 |
| 文件大?。?/td> | 264K |
| 代理商： | TDA8754HL/21 |
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9397 750 14984
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 06 — 16 June 2005
16 of 57
Philips Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msps
Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO
signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic 0 to
a logic 1 a left move is obtained, also the timing relationship between HSYNCO, DEO and
CKDATA stays unchanged. An even number of pixel moves is done by changing the value
of HBACKL and HSYNCL. The correct combination of bits HBACKL, HSYNCL and
SCHCKREFO places the rst active pixel at the beginning of the screen with always the
correct phase relationship between outputs DEO, HSYNCO and CKDATA.
Bit HSOSEL should be set to a logic 0 only after the PLL is stable, so only after the video
standard has been found and correct PLL parameters have been set in the TDA8754. Bit
HSOSEL should be set to a logic 1 to have a stable HSYNCO signal during the video
recognition. The video standard can be recognized by using the signals FIELDO,
VSYNCO and HSYNCO. The phase relation between CKDATA and HSYNCO (or DEO) is
undened if bit HSOSEL = 1.
8.4 PLL
The ADCs are clocked by either the internal PLL locked to the reference clock (Hsync
from input or Hsync from sync separator) or to an external clock connected to pin CKEXT.
This selection is performed via the I2C-bus by setting bit CKEXT. To use the external
clock, bit CKEXT must be reset to logic 1.
The PLL phase frequency detector can be disconnected during the frame yback (vertical
blanking) or the unavailability of the Ckref signal by using the coast function. The coast
signal can be derived from the VSYNC1(2) input, from the Vsync extracted by the sync
separator or from the coast input. The coast function can be disabled with bit COE.
The coast signal may be active either HIGH or LOW by setting bit COS.
It is possible to control the phase of the ADC clock via the I2C-bus with the included digital
phase-shift controller. The phase register (5 bits) enables to shift the phase by steps of
11.25 deg.
The PLL also provides a CKDATA clock. This clock is synchronized with the data outputs
whatever the output mode is.
It is possible to delay the CKDATA clock with a constant delay (t = 2 ns compared to the
outputs) by setting bit CKDD = 1. Moreover, it is possible to invert this output by setting
bit CKDATINV = 1.
When the PLL reference signal comes from the separator, the PLL rising edge must be
preferably used in order to not use the PLL coast mode. It should be noted that the
HSYNCO output of the sync separator is always a mostly low signal, whatever is the
polarity of the composite sync input. The VSYNCO output signal of the sync separator is
also mostly low signal. It is at a high state during the vertical blanking.
8.5 Sync-on-green
When the SOG input is selected (bit SOGSEL = 1), the SOG charge pump current bits
SOGI[1:0] should be programmed in function of the input signal; see Table 5.
A hum remover is implemented in the SOG. It removes completely the hum perturbation
on the rst or second edge of the horizontal sync pulse for digital video input like VESA,
and on the second edge only for analog video input signal like TV or HDTV.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA8754EL/21 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| TDA8754HL/11 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| TDA8754EL/11 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| TDA8754HL/17 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| TDA8754EL/17/C1 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8754HL21BE-S | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 TRPL 8BIT VIDEO ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8754HL21BE-T | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 3X8 BIT VIDEO A/D-210 MSPS RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8754HL27BE-S | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 3X8 BIT VIDEO A/D-270 MSPS RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8755 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
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