參數(shù)資料
型號： TDA8754HL/21
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, LOW PROFILE, PLASTIC, SOT-486-1, MS-026, QFP-144
文件頁數(shù)： 38/57頁
文件大小： 264K
代理商： TDA8754HL/21
9397 750 14984
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 06 — 16 June 2005
43 of 57
Philips Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msps
GE(rms)
full-scale channel-to-channel
matching (RMS value)
minimum coarse gain;
code = 32
-
2.5
%
R, G and B clamp
Nclamp
clamp level accuracy
fCLK = 25 MHz, clamp code =
20
--1
bit
Phase-Locked Loop (PLL); see Table 76
JPLL(p-p)
long term PLL phase jitter
(peak-to-peak value)
fclk = 270 MHz; DR = 2160
-
390
480
ps
DR
divider ratio
100
-
4095
fPLL
output clock frequency
10
-
270
MHz
fref
reference clock frequency
15
-
150
kHz
step
number of phase shift steps
from drift
--2
step
phase shift step
-
11.25
-
deg
Analog-to-Digital Converters (ADCs); minimum coarse gain
fs(max)
maximum sampling frequency
270
-
MHz
INL
integral non-linearity
fclk = 270 MHz; fi = 10 MHz
-
±0.6
±1.3
bits
DNL
differential non-linearity
fclk = 270 MHz; fi = 10 MHz
-
±0.25
±0.6
bits
ENOB
effective number of bits
fclk = 270 MHz; fi = 10 MHz
-
7.6
-
bits
αct
crosstalk
fclk = 270 MHz
-
45
dB
S/N
signal-to-noise ratio
fclk = 270 MHz; fi = 10 MHz
-
48
-
dB
SFDR
spurious free dynamic range
fclk = 270 MHz; fi = 10 MHz
48
55
-
dB
THD
total harmonic distortion
fclk = 270 MHz; fi = 10 MHz
-
55
48
dB
Data timing; 10 pF load; see Figure 4
td(o)
output delay
-
4
5.2
ns
th(o)
output hold time
1.9
-
ns
tsu(o)
output setup time
-
6
ns
LV-TTL digital inputs and outputs
Input pins CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK and CLP
VIL
LOW-level input voltage
0
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
VCCD(TTL) V
Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO, HSYNCO,
VSYNCO, FIELDO, CLPO, CKREFO and CSYNCO
VOL
LOW-level output voltage
IOH = 1 mA
-
0.4
V
VOH
HIGH-level output voltage
IOL = 1 mA
2.4
-
V
Data clock output
Output pin CKDATA
fCKDATA(max)
maximum buffer frequency
-
140
-
MHz
Data outputs
Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO and CSYNCO
fdata(max)
maximum buffer frequency
-
70
-
MHz
Table 75:
Characteristics …continued
Tamb =25 °C unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
相關(guān)PDF資料
PDF描述
TDA8754EL/21 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208
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TDA8755T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface
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