參數(shù)資料
型號: TDA8754EL/17/C1
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208
封裝: 17 X 17 MM, 1.05 MM HEIGHT, PLASTIC, MO-192, SOT774-1, LBGA-208
文件頁數(shù): 28/57頁
文件大小: 259K
代理商: TDA8754EL/17/C1
TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
34 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.16 Output register
1
VSOINVRGB
enables the output VSYNCO to be inverted
0 = non-inverted
1 = inverted
0
FIELDOINV
enables the output FIELDO to be inverted
0 = non-inverted
1 = inverted
Table 50.
INVERTER - inverter register (address 16h) bit description …continued
Bit
Symbol
Description
Table 51.
OUTPUT - output register (address 17h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
RGBSEL
TEN
AGCSEL1
AGCSEL0
BLKEN
DMXRGB
ODDARGB
SHIFTRGB
Reset
00000000
Access
WWWWWWWW
Table 52.
OUTPUT- output register (address 17h) bit description
Bit
Symbol
Description
7
RGBSEL
denes which RGB input will be used
0 = input 1
1 = input 2
6
TEN
enables the track and hold operating mode to be selected
0 = mode enable; must be set to logic 0 for proper operation
1 = mode disable
5 to 4
AGCSEL[1:0]
dene the output on pin AGCO
00=RAGC
01=GAGC
10=BAGC
11 = not used
3
BLKEN
inhibits the blanking mode during clamp
0 = blanking active; during the blanking period, the RGB outputs of the ADC are xed at
the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater
or equal to 0, or forced to 0 if these values are negative.
1 = blanking not active
2
DMXRGB
determines whether all pixels go to port A or if pixels go alternately to port A and B. The
maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode.
0 = port A
1 = port A and B
1
ODDARGB
denes the parity of the pixels
0 = even pixel on port A
1 = odd pixel on port A
0
SHIFTRGB
denes output on port A and B
0 = synchronous
1 = interleaved
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