參數(shù)資料
型號: TDA8034HN/C1
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC24
封裝: 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-1, HVQFN-24
文件頁數(shù): 30/30頁
文件大?。?/td> 265K
代理商: TDA8034HN/C1
TDA8034HN
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1. — 5 September 2011
9 of 30
NXP Semiconductors
TDA8034HN
Smart card interface
8.7 Activation sequence
The following device activation sequence is applied when using an external clock; see
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
Calculation of the time delays is as follows:
t1 = t0 + 384 1fosc(int)low
t2 = t1
t3 = t1 + 17T / 2
t4 = driven by host controller; > t3 and < t5
t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (1
fosc(int)high); t3 is called td(start) and t5 is called td(end).
Fig 6.
Shutdown and Deep shutdown mode activation/deactivation
001aal139
shutdown
CMDVCCN
VCC_SEL1
VCC_SEL2
mode
(internal pin)
OFFN
PRESN
VCC
shutdown
deactivation
sequence
shutdown
debounce
deep shutdown
activation
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