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參數(shù)資料
| 型號： | TDA7513T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 接收器 |
| 英文描述： | AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大?。?/td> | 845K |
| 代理商： | TDA7513T |
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Functional description
TDA7513T
3.3
PLL and IF counter section
The IC contains a frequency synthesizer and a loop filter for the radio tuning system. Only
one VCO is required to build a complete PLL system for FM and AM upconversion. For auto
search stop operation an IF counter system is available.
3.3.1
PLL frequency synthesizer block
The counter works in a two stages configuration. The first stage is a swallow counter with a
two-modulus (32/33) precounter. The second stage is an 11-bit programmable counter. The
circuit receives the scaling factors for the programmable counters and the values of the
reference frequency via I2C bus. The reference frequency is generated by an adjustable
internal (XTAL) oscillator followed by the reference divider. The reference and step-
frequencies are independently selectable (RC, PC). The phase-frequency detector outputs
switches the programmable current source. The loop filter integrates the latter to a DC
voltage. The current source values is programmable with 6 bits received via I2C bus (A, B,
CURRH, LPF). To minimize the noise induced by the digital part of the system, a special
guard area is implemented. The loop gain can be adjusted for different conditions by setting
the current values of the chargepump generator.
3.3.2
Frequency generation for phase comparison
The VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a
5-bit divider (A). A 5-bit register (PC0 to PC4) controls this divider. The output of the
prescaler is connected to an 11-bit divider (B), controlled by an 11-bit PC register (PC5 to
PC15).
The following expressions relate the divider output frequency (fSYN, forced by the loop to
equal the reference frequency at the phase comparator input fREF) to the VCO frequency
(fVCO) and to the crystal oscillator frequency (fXTAL):
fXTAL = (R+1) x fREF
fVCO = [33 x A + (B + 1 - A) x 32] x fREF
fVCO = (32 x B + A + 32) x fREF
Important: For correct operation: A
≤32; B ≥A
3.3.3
Three state phase comparator
The phase comparator generates a phase error signal according to phase difference
between fSYN and fREF. This phase error signal drives the charge pump current generator.
3.3.4
Charge pump current generator
This system generates correction current pulses with a polarity and a duration dictated by
the phase error signal. The current absolute values are programmable through register A for
high current and register B for low current.
The charge pump operates in high current mode when the phase difference between
between fSYN and fREF is high. The switch back to low current mode can be done either
automatically as a function of the inlock detector output (setting bit LDENA to "1") or via
software.
After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay
multiple of 1/fREF, the chargepump is forced in low current mode. A new PLL divider
programming by I2C bus will switch the chargepump into high current mode.
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