參數(shù)資料
型號: TDA7500ATR
廠商: STMICROELECTRONICS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 34/41頁
文件大小: 431K
代理商: TDA7500ATR
TDA7500A
4/40
14
CLKIN
I
Clock Input pin (Input). Clock from external digital audio source
to synchronize the internal PLL.
15
AVDD
Supply pin dedicated to the PLL.
16
XTI
I
Crystal Oscillator Input (Input). External Clock Input or crystal
Oscillator input.
17
XTO
O
Crystal Oscillator Output (Output). Crystal Oscillator output
drive.
18
AGND
Ground pin dedicated to the PLL.
19
RDSINT/DSP1_GPIO4
O
RDS bit/block interrupt (Output)/General Purpose I/O (Input/
Output). Provides an interrupt to the main micro. Optionally it
can be used as general purpose I/O controlled by DSP1.
20
RDSARI_SCK/DSP1_GPIO3
O
SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O
(Input/Output). If SPI interface is enabled, behaves as SPI bit
clock. Optionally it provides the ARI indication bit. Optionally it
can be used as general purpose I/O controlled by DSP1.
21
RDSQAL_SO/DSP1_GPIO2
O
SPI Slave Output Serial Data (Output)/RDS Bit Quality (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Output. Optionally it provides the RDS serial data
quality information. Optionally it can be used as general purpose
I/O controlled by DSP1.
22
RDSDAT_SI/DSP1_GPIO1
I
SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Input. Optionally it provides the RDS serial data
stream. Optionally it can be used as general purpose I/O
controlled by DSP1.
23
RDSCLK_SS/DSP1_GPIO0
I
SPI Chip Select (Input)/RDS Bit Clock (Output)/General
Purpose I/O (Input/Output). If SPI is enabled, behaves as Chip
Select line for SPI bus. Optionally it provides the 1187.5Hz RDS
Bit Clock. Optionally it can be used as general purpose I/O
controlled by DSP1.
24
INT
I
External interrupt line (Input). When this line is asserted low, the
DSP may be interrupted. Acts as IRQA line of DSP0 core.
25
CGND1
Ground pin dedicated to the digital circuitry.
26
CVDD1
Supply pin dedicated to the digital circuitry.
27
SCRCCD
I
SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital
audio source like a CD.
28
SCRMD
I
SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital
audio source like a MD.
29
DSRA<7>
I/O
DSP SRAM Data Lines<7> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 7.
30
DSRA<6>
I/O
DSP SRAM Data Lines<6> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 6.
Name
Type
Description
PIN DESCRIPTION (continued)
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