參數(shù)資料
型號： TDA5221
廠商： INFINEON TECHNOLOGIES AG
英文描述： ASK/FSK Single Conversion Receiver
中文描述： 詢價/ FSK信號單一轉(zhuǎn)換接收器
文件頁數(shù)： 43/44頁
文件大?。?/td> 705K
代理商： TDA5221
Reference
5 - 10
TDA 5221
preliminary
Wireless Components
Target Specification, October 2001
Table 5-4 AC/DC Characteristics with T
AMB
= -40
°
C ... + 105
°
C, V
VCC
= 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
1
Maximum Datarate
DR
max
100
kBps
NRZ, 20pF capaci-
tive loading
I
2
LOW output voltage
V
SLIC_L
0
0.1
V
3
HIGH output voltage
V
SLIC_H
V
S
-
1.5V
V
S
-1V
V
S
-
0.5V
V
Slicer, Negative Input (PIN 20)
1
Precharge Current Out
I
PCH_SLN
-100
-220
-300
μA
see Section 4.7
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
I
load
-400
-850
-1400
μA
2
Internal resistive load
R
t.b.d
446
t.b.d.
k
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
1
Operating frequency
f
CRSTL
t.b.d.
11
MHz
fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
V
MSEL
1.4
4
V
or open
2
FSK Mode
V
MSEL
0
0.2
V
3
Input bias current MSEL
I
MSEL
t.b.d.
-11
t.b.d.
μA
MSEL tied to GND
FSK DEMODULATOR
1
Demodulation Gain
G
FMDEM
105
140
245
μV/
kHz
2
Useable IF Bandwidth
BW
IFPLL
10.4
10.7
11
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDN
ON
0
0.8
V
2
Powerdown Mode Off
PWDN
Off
2.8
V
S
V
3
Start-up Time until valid
signal is detected at IF
T
SU
1
ms
PLL DIVIDER
Signal FSEL (PIN 11)
1
Overal divison ratio 32
V
FSEL
1.4
4
V
or open
2
Overal division ratio
32.25
V
FSEL
0
0.2
V
or tied to GND
3
Input bias current FSEL
I
FSEL
t.b.d.
-11
t.b.d.
μA
FSEL tied to GND
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