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參數(shù)資料
| 型號： | TDA5221 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ASK/FSK Single Conversion Receiver |
| 中文描述： | 詢價(jià)/ FSK信號單一轉(zhuǎn)換接收器 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 705K |
| 代理商： | TDA5221 |
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Applications
4 - 3
TDA 5221
preliminary
Wireless Components
Target Specification, October 2001
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the
3VOUT
pin is capable of driving up to
50μA, but that the
THRES
pin input current is only in the region of 40nA. As the
current drawn out of the
3VOUT
pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600k
in order to yield 3V at the
3VOUT
pin. R1
can thus be chosen as 240k
, R2 as 360k
to yield an overall
3VOUT
output
current of 5μA
1
and a threshold voltage of 1.8V
Note:
If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the
THRES
pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES
pin, such as a short to the
3VOLT
pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the
THRES
, such
as a short to ground.
As stated above the capacitor connected to the
TAGC
pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20k
resistor in series with the 3.1V internal voltage source
L
i
0
0.5
1
1.5
2
2.5
3
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
U
T
R
L
i
RSSI Level
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