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參數(shù)資料
| 型號： | TDA4887PS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 160 MHz bus-controlled monitor video preamplifier |
| 中文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-24 |
| 文件頁數(shù)： | 23/68頁 |
| 文件大?。?/td> | 425K |
| 代理商： | TDA4887PS |
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2001 Oct 19
23
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video
preamplifier
TDA4887PS
26.
Control bit FPOL = 0
: the internal feedback reference voltages for DC control act under I
2
C-bus control; subaddress
07H (channel 1), 08H (channel 2) and 09H (channel 3); bit resolution 0.4% of voltage range. Rising values of the data
bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs
(pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs
(pins 23, 20 and 17) during output clamping (V
HFB
> 3.5 V) in closed feedback loop. The feedback loop remains
operative at reference black levels between the specified values of V
o(n)bl(ref)(min)
and V
o(n)bl(ref)(max)
.
Control bit BRI = 1
: the internal feedback reference voltages can be shifted under I
2
C-bus control which allows easy
brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage
shift range). The superimposition of internal feedback reference and brightness control leads to a voltage output
range of 5.8 to 2.5 V.
27. Slow variations of video supply voltage V
CRT
will be suppressed at the CRT cathode by the clamping feedback loop.
A change of V
CRT
with 5 V leads to a specified change of the cathode voltage.
28. To adapt to different types of post amplifier, the internal feedback reference voltage for AC coupling (control bit
FPOL = 1) acts under I
2
C-bus control; subaddress 0AH (bit resolution 14.29%). The internal feedback reference
voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (V
HFB
> 3.5 V); reference
black level or pedestal black level.
29. The DAC output voltages act under I
2
C-bus control for control bit FPOL = 1; subaddress 07H (FB/R
1
), 08H (FB/R
2
)
and 09H (FB/R
3
); bit resolution 0.4% of voltage range respectively. Using an inverting amplifier for DC restoration,
rising values of the data bytes, e.g. 00H to FFH, correspond to changing the light output from dark to bright.
With control bit BRI = 1 the DAC output voltages can be shifted under I
2
C-bus control which allows easy brightness
control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range).
The superimposition of black level control and brightness control leads to a voltage output range of 5.8 to 2.5 V.
30. All adjustments via the I
2
C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I
2
C-bus
transmission in buffered mode. Conversely the adjustments via the I
2
C-bus will take effect immediately in
direct mode.
The timing of I
2
C-bus transmissions in buffered mode is related to the vertical blanking. See Section 7.6 and note 7
for specification of vertical blanking input (pin 5).
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