參數(shù)資料
型號(hào)： TDA4887PS
廠商： NXP SEMICONDUCTORS
元件分類： 音頻／視頻放大
英文描述： 160 MHz bus-controlled monitor video preamplifier
中文描述： 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24
封裝： 0.400 INCH, PLASTIC, SDIP-24
文件頁(yè)數(shù)： 13/68頁(yè)
文件大小： 425K
代理商： TDA4887PS
2001 Oct 19
13
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video
preamplifier
TDA4887PS
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); V
P
= V
P1,2,3
= 8 V (pins 7, 21, 18 and 15);
T
amb
= 25
°
C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22,
19 and 16); reference black level (V
bl(ref)
) approximately 0.7 V; nominal setting for brightness; maximum settings for
OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (V
LIM
≥
5 V); no OSD fast blanking
(pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
P
V
P(SO)
supply voltage (pin 7)
supply voltage threshold at
pin 7 at which signal outputs
are switched off
supply current (pin 7)
supply voltage; channels 1,
2 and 3 (pins 21, 18 and 15)
supply current; channels 1,
2 and 3 (pins 21, 18 and 15)
7.6
6.8
8.0
7.0
8.8
7.2
V
V
note 1
I
P
V
P(n)
note 4
7.6
25
8.0
30
8.8
mA
V
I
P(n)
pins 22, 19 and 16
open-circuit;
V
bl(n)(ref)
=
0.7 V;
notes 4 and 5
20
25
mA
Input clamping and vertical blanking input, validation of buffered I
2
C-bus data (CLI; pin 5)
V
CLI
input clamping and vertical
blanking input signal
notes 6 and 7
no vertical blanking,
no input clamping
vertical blanking,
no input clamping
input clamping,
no vertical blanking
V
CLI
= 1 V
pin 5 connected to ground;
note 8
V
CLI
=
0.1 V; note 8
note 6; see Fig.7
0.1
+1.2
V
1.6
2.6
V
3.5
V
P
V
I
CLI
input current
80
0.2
45
30
μ
A
μ
A
250
135
100
75
μ
A
ns/V
t
r/f5
rise/fall time for input
clamping pulse; disable for
vertical blanking
width of input clamping
pulse
width of vertical blanking
pulse for validation of
buffered I
2
C-bus data
delay between leading edge
of vertical blanking pulse
and validation of buffered
I
2
C-bus data
t
W(CLI)
200
ns
t
W(I2C)(valid)
leading and trailing edge
threshold V
CLI
= 1.4 V;
note 7
I
2
C-bus buffered mode
transmission completed;
leading edge threshold
V
CLI
= 1.4 V; note 7;
see Fig.7
10
μ
s
t
d(I2C)(valid)
2
μ
s
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