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參數(shù)資料
| 型號： | TD7626FN |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 338K |
| 代理商： | TD7626FN |
TD7626F,TD7626FN
2001-03-01 4/14
PIN
No.
PIN NAME
FUNCTION
INTERFACE CIRCUIT
7
P6
Output can be controlled by setting
the band switch data.
The circuit configuration is open
collector output.
An A / D converter is built in. In READ
mode, five levels of applied voltage
can be read.
In TEST mode, outputs the reference
signal derived by dividing the crystal
OSC signal by the set divider ratio.
This allows operation to be checked.
10
P3
Basically used as the address setting
pin. The sub-address can be changed
by applied voltage.
Can be used as a band switch as
well, but incorporates resistance
(12k) for limiting current.
11
P0
Output can be controlled by setting
the band switch data. Incorporates
resistance (12k) for limiting current.
(Can also be used for setting the
prescaler in TEST mode.)
(Open collector output)
12
VCC
Power supply pin
―
13
14
RF input
RF bias
Prescaler input pins.
The circuit configuration is differential
input.
Differential reference bias pin 14 has
a built-in 15pF capacitor.
15
GND
Ground pin
―
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