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參數(shù)資料
| 型號： | TD7626FN |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 338K |
| 代理商： | TD7626FN |
TD7626F,TD7626FN
2001-03-01 3/14
TERMINAL FUNCTIONS
PIN
No.
PIN NAME
FUNCTION
INTERFACE CIRCUIT
1
NF
16
Charge pump output
Compares the phase of the input RF
signal against the frequency data and
feeds back its difference output from
the current pump.
2
X’tal OSCin
3
X’tal OSCout
Crystal oscillator pins to generate the
reference signal for the phase
comparator. Consist of the inverter
amp.
4
SDA
Normally used as input / output pins
for the I
2
C bus serial data.
In TEST mode, used as the input pin
for the signal to be compared by the
phase comparator.
5
SCL
Normally used as the I
2
C bus serial
clock input.
In TEST mode, used to input the
reference signal of the phase
comparator.
6
P7
8
P5
9
P4
Output can be controlled by setting
the band switch data.
The circuit configuration is open
collector output. Each pin has a
built-in comparator. The status of the
comparator can be checked in READ
mode.
In TEST mode, P7 is a counter output
which allows counter operation to be
checked.
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