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參數(shù)資料
| 型號： | TCM38C17IDLDL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QComboE FOUR-CHANNEL QUAD PCM COMBO |
| 中文描述： | QComboE四通道的Quad的PCM組合 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 314K |
| 代理商： | TCM38C17IDLDL |
TCM38C17IDL
QCombo
FOUR-CHANNEL (QUAD) PCMCOMBO
SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1)
PARAMETER
TEST CONDITION
MIN
MAX
–30
UNIT
16.67 Hz
50 Hz
–25
60 Hz
–23
Gain (voltage amplification) relative to gain at
1 02 kHz
1.02 kHz
Input amplifier set for unity gain,
Noninverting maximum gain output,
Input signal at ANLGIN is 0 dBm0
200 Hz
–1.8
–0.125
dB
300 Hz to 3 kHz
–0.15
0.15
3.3 kHz
–0.35
0.15
3.4 kHz
4 kHz
–1
–0.1
–14
receive filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 2)
PARAMETER
TEST CONDITION
MIN
MAX
0.15
UNIT
Below 20 Hz
20 Hz
0.15
200 Hz
–0.5
0.15
Gain (voltage amplification) relative to gain at 1.02 kHz
Input signal at PCMIN
is 0 dBm0
300 Hz to 3 kHz
–0.15
0.15
dB
3.3 kHz
–0.35
0.15
3.4 kHz
–1
–0.1
4 kHz
4.6 kHz and above
–14
–30
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN
NOM
MAX
UNIT
tc(MCLK)
tr
tf
tw(MCLK)
Clock period for MCLK 2.048 MHz systems
488.28
ns
Rise time for MCLK
30
ns
Fall time for MCLK
30
ns
Pulse duration for MCLK (see Note 8)
220
ns
Clock duty cycle [tw(MCLK)/tc(MCLK)] for MCLK
All nominal values are at VDD = 5 V, and TA = 25
°
C.
NOTE 7: FS clock must be phase-locked with MCLK.
45%
50%
55%
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