參數(shù)資料
型號(hào)： TCM38C17IDLDL
廠商： Texas Instruments, Inc.
英文描述： QComboE FOUR-CHANNEL QUAD PCM COMBO
中文描述： QComboE四通道的Quad的PCM組合
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 314K
代理商： TCM38C17IDLDL
TCM38C17IDL
QCombo
FOUR-CHANNEL (QUAD) PCMCOMBO
SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
system reliability and design considerations
(continued)
internal sequencing
On the transmit channel, digital output PCMOUT is held in the high-impedance state for approximately four
frames (500
μ
s) after power up. Frame sync must be applied to all four channels during this time. After this delay,
PCMOUT is functional and occurs in the proper timeslot. Valid digital information, such as for on/off hook
detection, is available almost immediately.
To further enhance system reliability, PCMOUT is placed in a high-impedance state approximately 20
μ
s after
an interruption of MCLK. This interruption could possibly occur with some kind of fault condition elsewhere in
the system.
power-down operation
To minimize power consumption, a power-down mode is provided for each channel. To power down a channel,
an external logic low signal is applied to the corresponding PDN terminal. In the power-down mode, the average
power consumption is reduced to an average of 1 mW/channel.
miscellaneous
TCM38C17IDL timing and voltage references are described in the following paragraphs.
data timing
The TCM38C17IDL uses the 2.048 MHz master clock input to step data into and out of the device. An 8-kHz
clock signal applied to the FS terminal sets the sampling frequency and indicates the beginning of data transfer.
When MCLK goes low while FS is high, the frame sync is recognized. The next eight rising edges of MCLK step
data out of PCMOUT, while data is received into PCMIN on the next eight falling edges of MCLK. It is
recommended that frame sync pulses be one MCLK period in duration, but it is permissible for them to last up
to seven MCLK periods from the recognition of the frame sync.
Frame syncs for channels 0 through 3 must occur sequentially. When all four channels are in use, the frame
syncs (downward edge of MCLK during frame sync high) must occur at nominal 64 MCLK pulse intervals,
making the frame syncs evenly distributed. When one or more channels are not in use, the active frame syncs
have greater timing flexibility, but still must be separated by a minimum of 64 MCLK periods (nominal 31.25
μ
s
with 2.048 MHz MCLK). See Figure 6.
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