參數(shù)資料
型號(hào)： TCM37C15AN
廠商： Texas Instruments, Inc.
英文描述： PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
中文描述： 的PCM組合，具有可編程增益控制
文件頁(yè)數(shù)： 8/23頁(yè)
文件大?。?/td> 351K
代理商： TCM37C15AN
TCM37C14A, TCM37C15A
PCMCOMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018B – JUNE 1996 – REVISED MAY 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (outputs not loaded) (unless otherwise noted) (continued)
transmit filter transfer function (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit absolute delay time to PCMOUT
fMCLK = 2.048 MHz,
Input to ANLGIN is 1.02 kHz at 0 dBm0
245
μ
s
f = 500 Hz to 600 Hz
170
Transmit differential envelope delay time
relative to transmit absolute delay time
f = 600 Hz to 1000 Hz
95
μ
s
f = 1000 Hz to 2600 Hz
45
f = 2600 Hz to 2800 Hz
105
Receive absolute delay time to PWRO+
fMCLK = 2.048 MHz, Digital input is digital milliwatt codes
f = 500 Hz to 600 Hz
190
μ
s
45
Receive differential envelope delay time
relative to transmit absolute delay time
f = 600 Hz to 1000 Hz
35
μ
s
f = 1000 Hz to 2600 Hz
85
f = 2600 Hz to 2800 Hz
110
16.67 Hz
–30
50 Hz
–25
60 Hz
–23
Gain (voltage amplification) relative to gain
at 1.02 kHz
Input amplifier set for unity gain,
Noninverting maximum gain output
Noninverting maximum gain out ut,
Input signal at ANLGIN is 0 dBm0
In ut signal at ANLGIN is 0 dBm0
200 Hz
–1.8
–0.125
dB
300 Hz to 3 kHz
–0.15
0.15
3.3 kHz
–0.35
0.15
3.4 kHz
4 kHz
–1
–0.1
–14
All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25
°
C.
receive filter transfer function (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
MAX
0.15
UNIT
Below 20 Hz
20 Hz
0.15
200 Hz
–0.5
0.15
Gain (voltage amplification) relative to gain at 1 02 kHz
Gain (voltage amplification) relative to gain at 1.02 kHz
Input signal at PCMIN is 0 dBm0
300 Hz to 3 kHz
–0.15
0.15
dB
3.3 kHz
–0.35
0.15
3.4 kHz
–1
–0.1
4 kHz
4.6 kHz and above
–14
–30
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
clock timing (see Figure 3
)
MIN
NOM
MAX
UNIT
tc(MCLK)
tr
tf
tw(MCLK)
Clock period, MCLK (2.048 MHz systems)
488
ns
Rise time, MCLK
5
30
ns
Fall time, MCLK
5
30
ns
Pulse duration, MCLK (see Note 7)
220
ns
Clock duty cycle [tw(CLK)/tc(CLK)], MCLK
NOTE 7: FSX CLK and FSR CLK must be phase-locked with MCLK.
45%
50%
55%
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