參數(shù)資料
型號(hào)： TCM37C14ADW
廠商： Texas Instruments, Inc.
英文描述： PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
中文描述： 的PCM組合，具有可編程增益控制
文件頁(yè)數(shù)： 3/23頁(yè)
文件大小： 351K
代理商： TCM37C14ADW
TCM37C14A, TCM37C15A
PCMCOMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018B – JUNE 1996 – REVISED MAY 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
’37C15A
15
’37C14A
19
AGND
Analog ground return for all internal voice circuits. AGND is connected internally to DGND.
ANLGIN
16
20
I
Analog input to transmit operational amplifier.
Selection between A-law and
μ
-law operation. When ASEL is connected to VBB, A-law is selected.
When ASEL is connected to VCC or ground,
μ
-law is selected.
Clock frequency selection. CLKSEL must be connected to VBB, VCC, or ground to select the master
clock frequency. When CLKSEL is tied to VBB, MCLK is 2.048 MHz. When it is tied to ground, MCLK
is at 1.544 MHz. When it is tied to VCC, MCLK is 1.536 MHz.
Digital ground for all internal logic circuits. DGND is internally connected to AGND.
ASEL
15
I
CLKSEL
10
I
DGND
11
13
FSR
10
12
I
Frame-synchronization clock input/time-slot enable for receive channel. The receive channel enters
the standby state when FSR is held low for 300 ms.
FSX
13
16
I
Frame-synchronization clock input/time-slot enable for transmit. The transmit channel enters the
standby state when FSX is held low for 300 ms.
GS0
8
9
I
Input for first bit of the programmable gain control circuitry. GS0 works in combination with GS1 to
simultaneously control transmit and receive gain, and controls power-down instruction. (See
Table 1 and 2 for control logic information.)
GS1
7
8
I
Input for second bit of the programmable gain control circuitry. GS1 works in combination with GS0
to simultaneously control transmit and receive gain, and controls power-down instruction. (See Table
1 and 2 for control logic information.)
GSR
6
7
I
Input to gain-setting network of the output power amplifier. Gain is set by external resistors with three
levels of programmable gain or attenuation control. (See Figure 6 and Figure 7 for recommended
configuration.)
GSX
19
23
O
Output terminal of internal uncommitted operational amplifier. Internally, GSX is the voice signal input
to the transmit filter.
MCLK
12
14
I
Master clock (input). For the TCM37C14A, the master clock frequency can be either 2.048 MHz,
1.544 MHz, or 1.536 MHz, and is selected by CLKSEL. MCLK for the TCM37C15A is 2.048 MHz.
PCMIN
9
11
I
Receive PCM input. PCM data is clocked in on PCMIN on eight consecutive negative transitions of
the receive data clock (MCLK).
PCMOUT
14
17
O
Transmit PCM output. PCM data is clocked out on PCMOUT on eight consecutive positive transitions
of the transmit data clock (MCLK).
PWRO+
2
2
O
Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance
loads directly in a differential or a single-ended configuration.
PWRO–
3
O
Inverting output of power amplifier. PWRO– is functionally identical with and complementary to
PWRO+.
RIN
3
4
I
Input to receive section amplifiers. (See Figure 6 and Figure 7 for recommended circuitry.)
RS1
4
5
Terminal for first gain-control resistor of the receive section. RS1 is selected through closure of the
first gain control switch. (See Figure 6 and Figure 7 for recommended circuitry.)
RS2
5
6
Terminal for second gain control resistor of the receive section. RS2 is selected through closure of
the second gain control switch. (See Figure 6 and Figure 7 for recommended configuration.)
TS1
18
22
Terminal for gain-control resistor on input of transmit section. TS1 is selected through closure of the
first gain-control switch. (See Figure 6 and Figure 7 for recommended configuration.)
TS2
17
21
Terminal for gain-control resistor on input of transmit section. TS2 is selected through closure of the
second gain-control switch. (See Figure 6 and Figure 7 for recommended configuration.)
TSX
18
O
Transmit channel time-slot strobe for the transmit channel (active low). TSX is an open drain output
and can be used as an enable signal for a 3-state output buffer.
VBB
VCC
1
1
Negative supply voltage. Input is –5 V
±
5%.
Positive supply voltage. Input is 5 V
±
5%.
20
24
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