參數(shù)資料
型號(hào)： TCA8418EYFPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, BGA25
封裝： 2 X 2 MM, 0.40 MM PITCH, DSBGA-25
文件頁(yè)數(shù)： 3/31頁(yè)
文件大?。?/td> 400K
代理商： TCA8418EYFPR
SDA
SCL
S
P
StartCondition
StopCondition
SDA
SCL
DataLine
Change
www.ti.com
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 5). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 6).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 5).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 7). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 5. Definition of Start and Stop Conditions
Figure 6. Bit Transfer
Copyright 2010, Texas Instruments Incorporated
11
Product Folder Link(s): TCA8418E
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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