參數(shù)資料
型號: TCA8418EYFPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, BGA25
封裝: 2 X 2 MM, 0.40 MM PITCH, DSBGA-25
文件頁數(shù): 28/31頁
文件大?。?/td> 400K
代理商: TCA8418EYFPR
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
www.ti.com
I
2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
FAST MODE
FAST MODE PLUS (FM+)
I2C BUS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fscl
I2C clock frequency
0
100
0
400
0
1000
kHz
tsch
I2C clock high time
4
0.6
0.26
ms
tscl
I2C clock low time
4.7
1.3
0.5
ms
tsp
I2C spike time
50
ns
tsds
I2C serial data setup time
250
100
50
ns
tsdh
I2C serial data hold time
0
ns
ticr
I2C input rise time
1000 20 + 0.1Cb
(1)
300
120
ns
ticf
I2C input fall time
300 20 + 0.1Cb
(1)
300
120
ns
tocf
I2C output fall time; 10 pF to 400 pF bus
300 20 + 0.1Cb
(1)
300
120
ms
I2C bus free time between Stop and
tbuf
4.7
1.3
0.5
ms
Start
I2C Start or repeater Start condition
tsts
4.7
0.6
0.26
ms
setup time
I2C Start or repeater Start condition hold
tsth
4
0.6
0.26
ms
time
tsps
I2C Stop condition setup time
4
0.6
0.26
ms
Valid data time; SCL low to SDA output
tvd(data)
1
0.9
0.45
ms
valid
Valid data time of ACK condition; ACK
tvd(ack)
1
0.9
0.45
ms
signal from SCL low to SDA (out) low
(1)
Cb = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)
STANDARD MODE, FAST
MODE, FAST MODE PLUS
(FM+)
UNIT
I2C BUS
MIN
MAX
tW
Reset pulse duration
120(1)
ms
tREC
Reset recovery time
120(1)
ms
tRESET
Time to reset
120(1)
ms
(1)
The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the
same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into
the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked
state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,
it will take anywhere from zero to 50 msec after the input transition to clock the signal into the first stage. Therefore, the total debounce
time may be as long as 100 msec. Finally, to account for a slow clock, the spec further guard-banded at 120 msec.
6
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA8418E
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