參數(shù)資料
型號(hào)： TCA8418EYFPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, BGA25
封裝： 2 X 2 MM, 0.40 MM PITCH, DSBGA-25
文件頁(yè)數(shù)： 10/31頁(yè)
文件大?。?/td> 400K
代理商： TCA8418EYFPR
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
www.ti.com
BIT
ADDRESS
REGISTER NAME(1)
REGISTER DESCRIPTION
7
6
5
4
3
2
1
0
UK2_
UK2
UK2_
UK2
UK2_
UK2
0×10
Unlock2
Unlock key 2
7
6
_5
4
3
_2
1
_0
UK1[6:0] contains the key number used to unlock key 1
UK2[6:0] contains the key number used to unlock key 2
A ‘0’ in either register means it is disabled. It lasts up to 7 seconds. Needs a second timer up to 31 seconds?
The keypad lock interrupt mask timer generates a first interrupt (K_INT) and then waits for a programmed time
before generating a second interrupt. A second interrupt can only be generated when a timer is enabled due to
an unlock sequence being pressed. The second interrupt is a key lock interrupt. When the interrupt mask timer is
disabled (‘0’), a key lock interrupt will trigger only when the correct and complete unlock sequence is completed.
GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0×11–0×13)
These registers are used to check GPIO interrupt status and are cleared on read.
GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0×14–0×16)
These registers show GPIO state when read for inputs and outputs.
GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0×17–0×19)
These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This is needed so
that the value can be written prior to being set as an output.
GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0×1A–0×1C)
These registers enable interrupts for GP inputs only.
Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0×1D–0×1F)
A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A '1' in any of these bits
puts the pin in keyscan mode and configured as a row or column accordingly.
GPI Event Mode Registers, GPI_EM1–3 (Address 0×20–0×22)
A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. A '1' in any of these
bits means it is part of the event FIFO.
GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0×23–0×25)
A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. A '1' in any of these bits
sets the pin as an output.
GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0×26–0×28)
A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in GPIO mode.
A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in GPIO mode.
Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0×29–0×2B)
This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits disables the debounce while a
bit value of ‘1’ enables the debounce.
BIT
ADDRESS
REGISTER NAME(1)
REGISTER DESCRIPTION
7
6
5
4
3
2
1
0
Debounce disable
C8D
N/A
C9DD
0×2B
DEBOUNCE_DIS 3
0: enabled
N/A
D
0
1: disabled
(1)
Only KEY_EVENT_A register is shown
18
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA8418E
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