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參數(shù)資料
| 型號： | TC94A29FB |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 282K |
| 代理商： | TC94A29FB |
TC94A29FAG/FB
2003-04-01
9
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
8
MV
DD
9
MV
SS
Power supply pins for
controller block
Power supply pins for the controller block.
Normally, V
DD
3.0 to 3.6 V.
When only the CPU operates (when the
75-kHz/32.768-kHz oscillator is used), it can
operate at
V
DD
1.8 to 3.6 V.
In the backup state (when the CKSTP
instruction is executed), current dissipation
decreases (10 A or below), allowing the power
supply voltage to be reduced to 1.0 V.
Raising the voltage on MVDD pin from 0 V to
1.8 V or higher triggers a system reset, causing
the program to start from address 0 (power-on
reset).
(Note) At power-on reset operation, allow 1 ms
to 50 ms while the device power supply
voltage rises.
(Note) The backup current is the total of
currents for CV
DD
, MV
DD
and DV
DD
.
17
PDO
Output pin for a phase error signal between the
EFM and PLCK signals.
Drives one of four values: AV
DD
, Hi-Z,
V
REF
, AV
SS
18
TMAX
TMAX detection result output pin.
Longer than specified cycle: Drives a high
level (AV
DD
)
Shorter than specified cycle: Drives a low
level (AV
SS
)
Within specified cycle: Hi-Z
19
LPFN
Inverted input pin for PLL low-pass filter
amplifier.
20
LPFO
Output pin for PLL low-pass filter amplifier.
21
VCOF
VCO filter pin
22
AV
SS
CD processor control
input/output pin
Ground pin for analog block
MV
DD
MV
SS
AV
DD
AV
SS
VCO
V
REF
AV
DD
LPFN
LPFO
V
REF
VCOF
AV
DD
V
REF
R
out4
AV
SS
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