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參數(shù)資料
| 型號： | TC94A29FB |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 282K |
| 代理商： | TC94A29FB |
TC94A29FAG/FB
2003-04-01
2
4-bit Microcontroller
Program memory (ROM): 16 bits 8 Ksteps
Data memory (RAM): 4 bits 512 words
Instruction execution time: 1.42 s, 40 s, 91.6 s, TOSC 3 (Every instruction consists of a single word.)
Crystal oscillator frequency: 16.9344 MHz, 75 kHz, 32.768 kHz, CR oscillation frequency
Stack levels: 6
AD converter: 6 bits 4 channels
LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 64 segments (max.)
I/O ports: CMOS I/O ports: 26 (max.)
N-channel open-drain I/O ports (for up to 5.5 V): 3 (max.)
Timer/counter: 8 bits (timer mode, pulse width detector and measure function)
General-purpose counter: 20 bits, 0.1 MHz to 20 MHz, Vin 0.2 Vpp (min.), input amplifier incorporated
Serial interface module: 1 port 2 channel supporting 2/3-line method or UART
(two input channels)
Four buzzer types: 0.75 kHz, 1 kHz, 1.5 kHz, and 3 kHz
Four modes: continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz intervals
Interrupts: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer)
Back-up mode: Four types: CD standby (CD processor stopped)
Clock stop (oscillator stopped)
Hardware wait (only crystal oscillator in operation)
Software wait (CPU in intermittent operation)
Reset function: Power-on reset circuit, supply voltage detector (detection voltage 1.5 V typ.)
CD Processor
Reliable sync pattern detection, sync signal protection and interpolation
Built-in EFM demodulator and subcode decoder
High-correction capability using Cross Interleave Read Solomon Code (CIRC) logical equation
C1 correction: dual
C2 correction: quadruple
Jitter absorption capability of 6 frames
Built-in 16 KB RAM
Built-in digital output circuit
Built-in L/R independent digital attenuator
Bilingual audio output
Audio output: 32fs, 48fs or 64fs selectable
Subcode Q data is read-timing free and can be driven out in sync with audio data.
Built-in data slicer and analog PLL (adjustment-free VCO used) circuit
Automatic adjustment of loop gain, offset, and balance at focus servo and tracking servo
Built-in RF gain auto-adjusting circuit
Built-in digital equalizer for phase compensation
Supports different pickups using on-chip digital equalizer coefficient RAM.
Built-in focus and tracking servo control circuit
Search control supports all modes and realizes high-speed, stable search.
Lens kick and feed kick use speed control method.
Built-in AFC and APC circuits for disc motor CLV servo
Built-in defect/shock detector
Built-in 8 times over-sampling digital filter and 1-bit DA converter
Built-in analog filter for 1-bit DA converter
Built-in zero-data detection output circuit
Supports double-speed operation.
Note:
Output pins for subcode Q data and audio data have multiplexed functions for controller-dedicated pins. The
function of each pin can be switched by program.
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