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參數(shù)資料
| 型號： | TC9332F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP60 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-60 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 613K |
| 代理商： | TC9332F |
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TC9332F
2002-02-06
7
(2)
The channel clock, bit clock and data format for data outputs SDO0~2 are selected by LROS0~2,
BCOS02 and SOFMT0~1 of control register 2 (CNT-R2).
Table 2 (a), (b), and (c) show setting modes for data outputs SDO0-2.
Table 2 (a)
Setting modes for data output SDO0
(*: Don't care)
Control Register
Formats for Data Output SDO0
CNT-R2
CNT-R1
LROS0
BCOS0 SOFMT0 LROS2
EBCS
Data
Bit Clock
Channel Clock
Data Format
0
*
0
16 bit
32 fs (FS32 terminal)
Internally generated
LR terminal
Internally
generated
MSB first
0
1
0
*
0
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally
generated
MSB first, effective
data after the change
point of LRCK
*
0
*
1
16 bit
32 fs (FS32 terminal)
1/ 2 of EBCI0 (64 fs)
ELRO terminal
Internally
generated
MSB first
*
1
0
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally
generated
(Note 1)
MSB first, effective
data after the change
point of LRCK
(8 clock shift output)
16 bit
32 fs
MSB first
48 fs
1
*
0
*
0
24 bit
64 fs
EBCO
terminal
Externally
input
ELRO terminal
Externally
input
MSB first, effective
data after the change
point of LRCK
16 bit
48 fs
1
*
1
0
24 bit
64 fs
EBCO
terminal
Externally
input
ELRO terminal
Externally
input
MSB first, effective
data after the change
point of LRCK
(8 clock shift output)
Note 1: Clock output from LR terminal is input to ELRO terminal.
Table 2 (b)
Setting modes for data output SDO1
(*: Don't care)
Control Register
Formats for Data Output SDO1
CNT-R2
CNT-R1
LROS1
BCOS1 SOFMT1 LROS2
EBCS
Data
Bit Clock
Channel Clock
Data Format
0
*
0
16 bit
32 fs (FS32 terminal)
Internally generated
LR terminal
Internally
generated
MSB first
0
1
0
*
0
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally
generated
MSB first, effective
data after the change
point of LRCK
*
0
*
1
16 bit
32 fs (FS32 terminal)
1/ 2 of EBCI0 (64 fs)
ELRO terminal
Internally
generated
MSB first
*
1
0
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally
generated
(Note 1)
MSB first, effective
data after the change
point of LRCK
(8 clock shift output)
16 bit
32 fs
MSB first
48 fs
1
*
0
*
0
24 bit
64 fs
EBCO
terminal
Externally
input
ELRO terminal
Externally
input
MSB first, effective
data after the change
point of LRCK
16 bit
48 fs
1
*
1
0
24 bit
64 fs
EBCO
terminal
Externally
input
ELRO terminal
Externally
input
MSB first, effective
data after the change
point of LRCK
(8 clock shift output)
Note 1: Clock output from LR terminal is input to ELRO terminal.
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