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參數(shù)資料
| 型號： | TC9332F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP60 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-60 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 613K |
| 代理商： | TC9332F |
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TC9332F
20
External interrupt register (XINTR) (Note 12)
The external interrupt register sets data in IFF2-0, which are allocated to the conditional jump
flag (F) field. (3 bit)
Flag Field
IFF2
IFF1
IFF0
D2
D1
D0
Off
0
Off
On
0
1
Off
On
Off
0
1
0
On
Off
1
0
Note 12: XINTR data are read synchronously with the SYNC signal.
Break address (BRKAR) register (Note 13)
This register sets the break address. Continuous comparison is made with the program counter
(PC) and when BRKRQ of the control register is on, program execution is stopped. Since DBUS
data are fetched to IFDOR when the value of the PC matches, it is possible to turn BRKRQ off
and read the internal data while program execution is in progress. (10 bit)
Note 13: Data can be set in BRKAR asynchronously with the SYNC signal.
Loop counter compare reference register (LCR) (Note 14)
When reading break or DBUS data, either of loop counters LC0 or LC1 is being compared along
with the PC value, this register stores the value of the loop counter to be compared. (8 bit)
Which of the loop counters is being compared is set by LCSEL of control register 0 (CNT-R0).
When break or DBUS data have been read, LCR is automatically decremented by 1.
Note 14: Data can be set in LCR asynchronously with the SYNC signal.
Interface data output register (IFDOR)
This is a buffer register that can read DBUS data. (24 bit)
The microcontroller can read data from IFDOR serially from the LSB. It is also possible to read
only the upper 16 bit by setting IFOS of control register 1 (CNT-R1).
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