參數(shù)資料
型號(hào)： TC9332F
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP60
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-60
文件頁數(shù)： 25/28頁
文件大小： 613K
代理商： TC9332F
TC9332F
2002-02-06
6
2.
Setting audio data input/output format (data, channel clock, and bit clock)
The 16 bit/24 bit serial data input/output channel clocks (LR, ELRI0~1 and ELRO0~2) and bit clocks (FS64,
FS32, EBCI0~1 and EBCO) can be either internally generated or externally input. The mode setting is
effected by the microcontroller interface (control register). Figure 4 shows the data input/output clock pulse
selector.
(1)
The channel clock, bit clock and data format for data inputs SDI0~1 are selected by LRIS0~1,
BCIS0~1 and SIFMT0~1 of control register 2 (CNT-R2). Table 1 (a) and (b) show setting modes for
data inputs SDI0~1.
Table 1 (a)
Setting modes for data input SDI0
Control Register 2
(CNT-R2)
Format for Data Input SDI0
LRIS0
BCIS0
SIFMT0
Data
Bit Clock
Channel Clock
Data Format
0
MSB first
0
1
16 bit
32 fs (FS32 terminal)
Internally generated
LR terminal
Internally generated
LSB first
0
1
0
MSB first, effective data before
the change point of LRCK
0
1
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally generated
LSB first, effective data before
the change point of LRCK
1
0
MSB first
1
0
1
16 bit
32 fs (EBCI0 terminal)
Externally input
terminal
ELRI0 terminal
Externally input
terminal
LSB first
1
0
MSB first, effective data before
the change point of LRCK
1
24 bit
48/64 fs
(EBCI0 terminal)
Externally input
terminal
ELRI0 terminal
Externally input
terminal
LSB first, effective data before
the change point of LRCK
Table 1 (b)
Setting modes for data input SDI1
Control Register 2
(CNT-R2)
Format for Data Input SDI1
LRIS1
BCIS1
SIFMT1
Data
Bit Clock
Channel Clock
Data Format
0
MSB first
0
1
16 bit
32 fs (FS32 terminal)
Internally generated
LR terminal
Internally generated
LSB first
0
1
0
MSB first, effective data before
the change point of LRCK
0
1
24 bit
64 fs (FS64 terminal)
Internally generated
LR terminal
Internally generated
LSB first, effective data before
the change point of LRCK
1
0
MSB first
1
0
1
16 bit
32 fs (EBCI1 terminal)
Externally input
terminal
ELRI1 terminal
Externally input
terminal
LSB first
1
0
MSB first, effective data before
the change point of LRCK
1
24 bit
48/64 fs
(EBCI1 terminal)
Externally input
terminal)
ELRI1 terminal
Externally input
terminal
LSB first, effective data before
the change point of LRCK
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