參數(shù)資料
型號(hào)： TC90A92AFG
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 23/34頁
文件大小： 459K
代理商： TC90A92AFG
TC90A92AFG
3. Terminal description
Pin
No.
Pin Name
Function
Durabl
e
voltage
(V)
I/O
Circuit
System
(Analog or
Digtal)
DC of
standard
operation
iuj
Analog signal
effective level
iVp-pj
1
VDDPLL
Power supply for X8 PLL circuit
2.5
VDD
Analog
2.5
-
2
PLLIN
Input terminal of X8 PLL circuit
2.5
IN
Analog
1.25
0.5`VDDPLL*0.8
3
VCOFIL
Filter terminal for X8 PLL circuit
2.5
Bypass
Analog
1.2
-
4
VSSPLL
GND for X8 PLL circuit
0
GND
Analog
0
-
5
VDDXO
Power supply for X’ tal OSC circuit
3.3
VDD
Digital
3.3
-
6
XOIN
X’ tal OSC circuit input terminal
3.3
IN
Digital
-
7
XOOUT
X’ tal OSC circuit output terminal
3.3
OUT
Digital
-
8
VSSXO
GND for X’ tal OSC circuit
0
GND
Digital
0
-
9
BUSSEL
Select IIC slave address
iLF
B0
HiF
B2j
3.3
IN
Digital
-
10 DVDD1
Power supply for Logic circuit
1.5
VDD
Digital
1.5
-
11 DIN9
Composite video signal digital input terminal
(MSB) iDIN0`DIN9F
input terminal for GRj
iIn case not use :DIN0-9 are connected to GNDj
3.3
IN
Digital
-
12 DIN8
Composite video signal digital input terminal
3.3
IN
Digital
-
13 DIN7
3.3
IN
Digital
-
14 DVSS12
GND for Logic circuit
0
GND
Digital
0
-
15 DIN6
Composite video signal digital input terminal
3.3
IN
Digital
-
16 DIN5
3.3
IN
Digital
-
17 DVDD2
Power supply for Logic circuit
1.5
VDD
Digital
1.5
-
18 DIN4
Composite video signal digital input terminal
3.3
IN
Digital
-
19 DIN3
3.3
IN
Digital
-
20 VSSRAM1
GND for internal DRAM
0
GNG
Digital
0
-
21 VDDRAM1
Power supply for internal DRAM
1.5
VDD
Digital
1.5
-
22 DIN2
Composite video signal digital input terminal
3.3
IN
Digital
-
23 DIN1
3.3
IN
Digital
-
24 VDDIO1
Power supply for I/O
3.3
VDD
Digital
3.3
-
25 DIN0
Composite video signal digital input terminal
3.3
IN
Digital
-
26 GC14IN
External 4fsc clock input terminal for
Using DIN0-9 terminal
iIn case not use : connect to GNDj
3.3
IN
Digital
-
27 VSSIO1
GND for I/O
0
GND
Digital
0
-
28 TESTIN
Clock terminal for Test mode
3.3
IN
Digital
0
-
29 TESTM0
Terminal for Test mode
3.3
IN
Digital
0
-
30 RESET
Reset terminal (Low :Reset Hi :normal)
3.3
IN
Digital
3.3
-
31 SDA
hhb
rc`
terminal (5V input possiblej
5
I/O
Digital
-
32 SCL
hhb
rbk
terminal (5V input possible)
5
IN
Digital
-
33 TESTM1
Terminal for Test mode
3.3
IN
Digital
0
-
34 TESTM2
3.3
IN
Digital
0
-
35 TESTM3
3.3
IN
Digital
0
-
36 DVDD3
Power supply for Logic circuit
1.5
VDD
Digital
1.5
-
37 TESTM4
Terminal for Test mode
3.3
IN
Digital
0
-
38 CSYNCIN
External composite Sync signal input
5
IN
Digital
0
-
39 DVSS3
GND for Logic circuit
0
GND
Digital
0
-
40 TESTM5
Terminal for Test mode
3.3
IN
Digital
0
-
41 TESTM6
3.3
IN
Digital
0
-
42 VDDIO2
Power supply for I/O
3.3
VDD
Digital
3.3
-
43 YOUT9
Digital video port outputiMSBj
i656/ 601 8bit modeF
YCbCr
601F
Yj
3.3
OUT
Digital
-
44 YOUT8
Digital video port output8
3.3
OUT
Digital
-
45 VSSIO2
GND for I/O
0
GND
Digital
0
-
46 YOUT7
Digital video port output7
3.3
OUT
Digital
-
47 YOUT6
Digital video port output6
3.3
OUT
Digital
-
48 YOUT5
Digital video port output5
3.3
OUT
Digital
-
49 YOUT4
Digital video port output4
3.3
OUT
Digital
-
50 VSSRAM2
GND for internal DRAM
0
GND
Digital
0
-
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