參數(shù)資料
型號(hào)： TC90A92AFG
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 10/34頁(yè)
文件大?。?/td> 459K
代理商： TC90A92AFG
TC90A92AFG
Sub
D7
D6
D5
D4
D3
D2
D1
D0
20H
ID1DLY
CCDSBH
The start timing of hc
P data slice
CCD start bit (H pulse period)
INIT:8BH
OOOO
F
Falling edge of H +PD
SW “ ` i300“
unitj
1111:30CK`0000:0CK (*CK=74ns)
21H
8OUTLSB
FIV
FON
Fixed [0]
m
0nFNormal
Fixed [1]
Fixed [0]
Fixed [1]
Field for
CCD slice
action
m
1nFON
0:EVEN
0:both field
INIT:80H
1:ODD
1:FIV
22H
EN_NOISEH_S
EN_NOISEH_W
SSMSB
AUTO
The horizontal start timing of S/N detection
The horizontal width of S/N detection
CCD slice
000F
35.7uS ` 100F
+40.5uS ` 111F
44uS
000F
10.2uS ` 100F
14.9uS ` 111F
18.5uS
Fixed to[1]
0:Auto
INIT:90H
(1step: 32/27MHz)
1:manual
23H
EN_NOISEV_S
EN_NOISEV_W
CLP
BYFOFF
BLMT
Adjustment for S/N detection start line
(Ex. NTSC mode)
S/N detection line number
16LSB limit
(output)
BSRY filter
V sepa.
Limit
2Fh(D3)=0, 000F
12th line`111F
18th line
00F
1HA
01F
2HA
10F
3HA
11F
4H
0:OFF
0:ON
0: 1/8
INIT:0AH
2Fh(D3)=1, 000F
7th line`111F
13th line
1:ON
1:OFF
1: 1/16
24H
HDPH
VDPH
Adjustment Horizontal phase
Adjustment vertical phase
INIT:00H
1000F
-1.185uS ` 0000F
0uS ` 0111F
+1.04uS
0000F
0H ` 1111F
+15H
25H
VPHS
CADSWREV
HDST
SELCK
VDOUT adjustment (601 mode)
Cb/Cr Input
HDOUT adjustment (601)
CKOUT frequency
110:384w
011:192w
000:0w
10:TEST
00:13.5MHz
111:don’t use
100:256w
001:64w
(See p.23)
11:13.5MHz
01::27MHz
INIT:03H
101:320w
010:128w
64W=64/27MHz=2.4uS
0F
Pin92=Cr- IN,
Pin94=Cb- IN
1F
Pin92=Cb- IN,
Pin94=Cr-IN
26H
PHPOLE
PVPOLE
PFPOLE
THRHV
INVCK
SEL_BLK
YOLEVEL
HHKIL
HDOUT
polarity
VDOUT polarity
Field
Polarity
H,V-OUT
through
CKOUT
Polarity
VBLK
Y Output
Level Select
Half H killer
0: positive
0:positive
0:656
0:positive
0:fixed value
0:x1.7
0F
OFF
INIT:18H
1:negative
1:through(601)
1:negative
1:through
1:x1.0
1F
ON
27H
EN_PIXH_S
EN_PIXH_W
Adjustment horizontal signal processing (start phase)
Adjustment horizontal signal processing (period)
INIT:00H
1000F
-1.185“ ` 0000F
center ` 0111F
+1.04“
1000F
-1.185“ ` 0000F
center` 0111F
+1.04“
28H
EN_PIXV_S
EN_PIXV_A
COMB KILL
Adjustment vertical signal processing (start phase)
0F
Manual
000F
OFF
011F
1`23H
110F
1`26H
0000F
line 10 ` 1111F
line 25
1F
Auto
001F
P`21H
100F
1`24H
111F
Auto
INIT:07H
010F
1`22H
101F
1`25H
(60:22H,50:23H)
29H
BFP_S
SEL_RDATA
Adjustment burst gate pulse start phas e
[0] Fix
Select read data
INIT:00H
0000F
}0 ` 0111F
+4.44“ (4/13.5M step)
(Reference the next page)
2AH
HBLK_S
HBLK_W
Adjustment HBLK start phase
Adjustment HBLK width
INIT:00H
1000F
-2.37“ ` 0000F
}0 ` 0111F
+2.07“
1000F
-2.37“ ` 0000F
}0 ` 0111F
+2.07“
2BH
FHST_S
FVST_S
Adjustment write timing for internal DRAM (horizontal)
Adjustment write timing for internal DRAM (vertical)
INIT:00H
1000F
-2.37“ ` 0000F
}0 ` 0111F
+2.07“
1000F
-8H ` 0000F
center ` 0111F
+7H
2CH
EXTCLP
SEL77
ACKDET
IIRFIL
Adjustment horizon position fine tuning for exterior clamp
i6.75MHz unitA
Width 2.2us Fixj
Pin77 Output
change
Detection
method change
Cb/Cr output filter selection
After input sync edge about +0.5s ` about +3s
0:ODD/EVEN
0:Level detection
00:Strong ` 10:weak
INIT:B2H
1000F
+0.5“ ` 0111F
+3“
1:Clamp pulse
1:Gain detection
11:OFF
2DH
GCSFT
FBCLAMP
GC Input DC shift
F/B CLAMP
000000:OA
1000000:-128lsb ` 0111111:+126lsb
0:Auto
INIT:01H
1:ON
2EH
HGCON12
HGCON21
Threshold from phase difference big to middle.
Threshold from phase difference middle to big.
INIT:48H
0000:OFF ` 1111:High
2FH
RBALT
RBCHG
YADFILON
NOISESEL
NOISEL
THRH_VD
ADC Output
The line select
S/N detection
VD out phase
Fixed [0]
13.5M Trap
Fixed [1]
for S/N
Line
(It is available
Fixed [1]
0:OFF 1:ON
detection
0 : CVBS/Y
when H-V is
Effective only
(See p.24)
1 : digital input
Non-standard)
at the time
0:standard
INIT:00H
of a CVBS input
1:V-sep phase
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