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參數(shù)資料
| 型號(hào)： | TC820CPL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 185K |
| 代理商： | TC820CPL |
15
TC820
3-3/4 A/D Converter with Frequency
Counter and Logic Probe
TC820-10 10/17/96
2001 Microchip Technology Inc.
DS21476A
Additional Features
The TC820 is available in 40-pin and 44-pin packages.
Several additional features are available in the 44-pin pack-
age.
EOC/HOLD
EOC/HOLD is a dual-purpose, bidirectional pin. As an
output, this pin goes low for 10 clock cycles at the end of
each conversion. This pulse latches the conversion data
into the display driver section of the TC820.
EOC/HOLD can be used to hold (or "freeze") the dis-
play. Connecting this pin to VDD inhibits the display update
process. Conversions will continue, but the display will not
change. EOC/HOLD will hold the display reading for either
analog-to-digital or frequency measurements.
The input/output structure of the EOC/HOLD pin is
shown in Figure 10. The output drive current is only a few
microAmps, so EOC/HOLD can easily be overdriven by an
open-collector logic gate, as well as a FET, bipolar transis-
tor, or mechanical switch. When used as an output, EOC/
HOLD will have a slow rise and fall time due to the limited
output current drive. A CMOS Schmitt trigger buffer is
recommended.
Connecting the LOGIC input to VDD places the TC820
in the logic probe mode. In this mode, the DP0/LO and
DP1/HI inputs control the LCD "low" and "high" annuncia-
tors directly. When DP1/HI is connected to VDD, the "high"
annunciator will turn on. When DP0/LO is connected to
VDD, the "low" annunciator and the buzzer will turn on. The
internal pull-downs on these pins are disabled when the
logic probe function is selected.
These inputs have CMOS logic switching thresholds.
For optimum performance as a logic probe, external level
shifters are recommended. See the applications section
for details.
BUZ IN
This input controls the TC820 on-chip buzzer driver.
Connecting BUZ IN to VDD will turn the buzzer on. There is
an external pulldown to DGND. BUZ IN can be used with
external circuitry to provide additional functions, such as a
fast, audible continuity indication.
Figure 10. EOC/HOLD Pin Schematic
4
500 k
≈
EOC/HOLD
DISPLAY
UPDATE
EOC
TC820
Overrange (OR), Underrange (UR)
The OR output will be high when the analog input
signal is greater than full scale (3999 counts). The UR
output will be high when the display reading is 380 counts
or less.
The OR and UR outputs can be used to provide an
auto-ranging meter function. By logically ANDing these
outputs with the inverted EOC/HOLD output, a single pulse
will be generated each time an underranged or overranged
conversion occurs (Figure 11).
VDISP
The VDISP input sets the peak-to-peak LCD drive volt-
age. In the 40-pin package, VDISP is connected internally to
DGND, providing a typical LCD drive voltage of 5VP-P. The
44-pin package includes a separate VDISP input for applica-
tions requiring a variable or temperature-compensated LCD
drive voltage. See the applications information for sug-
gested circuits.
EOC/HOLD
TC820
UR
OR
74HC132
*
Figure 11. Generating Underrange and Overrange Pulses
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