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參數(shù)資料
| 型號(hào)： | TC7MTX01FK |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 176K |
| 代理商： | TC7MTX01FK |
TC7MTX01FK
2002-03-18
11
DC Characteristics
(GND 0.0 V)
Ta 20°C
Ta 25°C
Ta 70°C
Characteristic
Symbol
Test Circuit
Min
Max
Min
Typ.
Min
Min
Max
Unit
High-level input voltage
V
IH
V
CC
2.7~3.3 V
2.0
2.0
2.0
V
Low-level input voltage
V
IL
V
CC
2.7~3.3 V
0.5
0.5
0.5
V
Hysteresis voltage
V
H
V
CC
3.0V
0.3
V
High-level output current
(DOUT)
I
OH
V
CC
3.0 V
V
OH
2.4 V
4.0
4.0
7.0
3.2
mA
Low-level output current
(DOUT)
I
OL
V
CC
3.0 V
V
OL
0.4 V
4.0
4.0
8.5
3.2
mA
Input current
I
IN
V
CC
3.3 V
V
IN
0 or 3.3 V
1.0
1.0
5.0
A
Three-state OFF leakage
current (DOUT)
I
OZ
V
CC
3.3 V
V
OUT
0 or 3.3 V
1.0
1.0
5.0
A
Pull-down resistance
(DIN, CK, STB, W/R)
R
PD
V
CC
2.7~3.3 V
4
10
20
k
Auto-reset release
voltage
V
RD
2.5
1.8
2.5
2.5
V
Static current dissipation
I
CC
V
CC
3.0 V (Note
2)
V
IN
V
CC
or GND
0.5
1.0
mA
Static current dissipation
I
REF
V
CC
2.8 V (Note2)
V
IN
V
CC
or GND
0.1
1.0
mA
Note2:
The current generated by setting the input pins with pull-down resistors to High is not included.
AC Characteristics
(Ta 25°C, V
CC
3.0 V, V
Ref
2.8 V, GND 0 V, C
L
50 pF, Input: t
r
, t
f
6 ns)
E
2
PROM
Write Timing (applies to Operation Modes 1, 3 and 4)
Characteristic
Symbol
Test Circuit
Typ
Limit
Unit
Minimum VP power-on timing time
(V.P power supply – STB input)
t
sv
Figure 1
0
ns
Minimum VP power-off timing time (STB input – V.P
power supply)
t
hv
Figure 1
0
ns
Minimum VP power supply cut-off pulse width
t
wL
Figure 1
10
s
Minimum set-up time (W/R input – STB input)
t
sw
Figure 1
0
ns
Minimum hold time (W/R input – STB input)
t
hw
Figure 1
40
ns
Minimum removal time (STB input – CK input)
t
rem
Figure 1
5
40
ns
Minimum write time (CK input – W/R input)
t
pws
Figure 1
10
ms
Minimum pulse width (STB input)
t
wL
Figure 1
10
s
Minimum clock cycle time (CK input)
t
cyc
Figure 1
0.2
2
s
Minimum clock pulse width (CK input)
t
wH
t
wL
Figure 1
0.1
1
s
Minimum set-up time (DIN input – CK input)
t
su
Figure 1
40
ns
Minimum hold time (DIN input – CK input)
t
h
Figure 1
5
40
ns
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