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參數(shù)資料
| 型號(hào)： | TC55VBM416AFTN55 |
| 廠商： | Toshiba Corporation |
| 英文描述： | CABLE 30 COND RIBBON WHT 100FT |
| 中文描述： | 1,048,576字由16位/ 2097152字的8位全的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 204K |
| 代理商： | TC55VBM416AFTN55 |
TC55VBM416AFTN55
2002-08-29 10/14
WRITE CYCLE 4 ( , LB
(See Note 4)
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
If CE1(or UB or LB) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the
outputs will remain at high impedance.
(3)
If CE1(or UB or LB) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
R/W
t
WC
t
AS
t
WR
t
WP
1
CE
VALID DATA IN
t
DS
t
DH
Hi-Z
Hi-Z
t
CW
CE2
t
BW
t
BE
t
COE
t
ODW
UB
, LB
t
CW
(See Note 5)
Address
A0~A19 (Word Mode)
D
OUT
I/O1~16 (Word Mode)
D
IN
I/O1~16 (Word Mode)
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