Choose CREF
參數(shù)資料
型號(hào)： TC530COI713
廠商： Microchip Technology
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ SUBSYSTEM 28SOIC
標(biāo)準(zhǔn)包裝： 1,600
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 17 b
采樣率（每秒）： 6.5
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 帶卷 (TR)
2007 Microchip Technology Inc.
DS21433C-page 13
TC530/TC534
EXAMPLE 5-4:
6.
Choose CREF and CAZ based on conversion
rate:
EXAMPLE 5-5:
7.
Calculate VREF.
EXAMPLE 5-1:
5.5
Power Supply Sequencing
Improper sequencing of the power supply inputs (VDD
vs. VCCD) can potentially cause an improper power-up
sequence to occur. See Section 5.6 “Circuit
Design/Layout Considerations”, Circuit Design/Lay-
out Considerations. Failing to insure a proper power-up
sequence can cause spurious operation.
5.6
Circuit Design/Layout
Considerations
1.
Separate ground return paths should be used
for the analog and digital circuitry. Use of ground
planes and trace fill on analog circuit sections is
highly recommended EXCEPT for in and around
the integrator section and CREF, CAZ (CINT,
CREF, CAZ, RINT). Stray capacitance between
these nodes and ground appears in parallel with
the components themselves and can affect
measurement accuracy.
2.
Improper sequencing of the power supply inputs
(VDD vs. VCCD) can potentially cause an
improper power-up sequence to occur in the
internal state machines. It is recommended that
the digital supply, VCCD, be powered up first.
One method of insuring the correct power-up
sequence is to delay the analog supply using a
series resistor and a capacitor. See Figure 5-1,
TC530/TC534 Typical Application.
3.
Decoupling capacitors, preferably a higher
value electrolytic or tantulum in parallel with a
small ceramic or tantalum, should be used
liberally. This includes bypassing the supply
connections of all active components and the
voltage reference.
4.
Critical components should be chosen for
stability and low noise. The use of a metal-film
resistor
for
RINT and Polypropylene or
Polyphenelyne Sulfide (PPS) capacitors for
CINT, CAZ and CREF is highly recommended.
5.
The inputs and integrator section are very high
impedance nodes. Leakage to or from these
critical nodes can contribute measurement
error. A guard-ring should be used to protect the
integrator section from stray leakage.
6.
Circuit assemblies should be exceptionally
clean to prevent the presence of contamination
from assembly, handling or the cleaning itself.
Minute conductive trace contaminates, easily
ignored in most applications, can adversely
affect the performance of high impedance
circuits. The input and integrator sections should
be made as compact and close to the TC53X as
possible.
7.
Digital and other dynamic signal conductors
should be kept as far from the TC53X’s analog
section as possible. The microcontroller or other
host logic should be kept quiet during a
measurement cycle. Background activities such
as keypad scanning, display refreshing and
power switching can introduce noise.
Note:
Microchip recommended capacitor:
Evox-Rifa p/n: SMR5 334K50J03L
Note:
Microchip recommended capacitor:
Evox-Rifa p/n: SMR5 224K50J02L4.
CINT
TINT
() 20 10
6
×
()
Vs 0.9
–
()
------------------------------------------
=
.066
() 20 10
6
–
×
()
=
4.1
---------------------------------------------------
.32
μF(use closest value: 0.33μF )
=
Conversions/sec = 1/(TAZ + TINT + 2TINT + 2ms)
= 1/(66ms + 66ms + 132ms + 2ms)
= 3.7 conversions/sec
from which CAZ = CREF = 0.22F (Table 6-1)
VREF
VS 0.9
–
() C
INT
() R
INT
()
2TINT
()
-----------------------------------------------------------
=
4.1
() 0.33 1
6
–
×
() 10
5
()
2 .066
()
--------------------------------------------------------
=
1.025V
=
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