參數(shù)資料
型號(hào)： TMS320C6205GHKA200
廠商： Texas Instruments
文件頁(yè)數(shù)： 1/73頁(yè)
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 288-BGA
標(biāo)準(zhǔn)包裝： 90
系列： TMS320C62x
類型： 定點(diǎn)
接口： McBSP，PCI
時(shí)鐘速率： 200MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.50V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 288-LFBGA
供應(yīng)商設(shè)備封裝： 288-BGA Microstar（16x16）
包裝： 托盤
其它名稱： 296-32744
TMS320C6205GHKA200-ND
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D High-Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6205
5-ns Instruction Cycle Time
200-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
1600 MIPS
D VelociTI Advanced-Very-Long-Instruction-
Word (VLIW) TMS320C62x
DSP Core
Eight Highly Independent Functional
Units:
Six ALUs (32-/40-Bit)
Two 16-Bit Multipliers (32-Bit Result)
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
D Instruction Set Features
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
D 1M-Bit On-Chip SRAM
512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
512K-Bit Dual-Access Internal Data
(64K Bytes)
Organized as Two 32K-Byte Blocks for
Improved Concurrency
D 32-Bit External Memory Interface (EMIF)
Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
52M-Byte Addressable External Memory
Space
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D Flexible Phase-Locked-Loop (PLL) Clock
Generator
D 32-Bit/33-MHz
Peripheral
Component
Interconnect (PCI) Master/Slave Interface
Conforms to:
PCI Specification 2.2
Power Management Interface 1.1
Meets Requirements of PC99
PCI Access to All On-Chip RAM,
Peripherals, and External Memory
(via EMIF)
Four 8-Deep x 32-Wide FIFOs for
Efficient PCI Bus Data Transfer
3.3/5-V PCI Operation
Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
Supports 4-Wire Serial EEPROM
Interface
PCI Interrupt Request Under DSP
Program Control
DSP Interrupt Via PCI I/O Cycle
D Two Multichannel Buffered Serial Ports
(McBSPs)
Direct Interface to T1/E1, MVIP, SCSA
Framers
ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
D Two 32-Bit General-Purpose Timers
D IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
D 288-Pin MicroStar BGA Package
(GHK and ZHK Suffixes)
D 0.15-m/5-Level Metal Process
CMOS Technology
D 3.3-V I/Os, 1.5-V Internal, 5-V Voltage
Tolerance for PCI I/O Pins
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright
2006, Texas Instruments Incorporated
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