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參數資料
| 型號： | TC33025VOETR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 16/18頁 |
| 文件大?。?/td> | 416K |
| 代理商： | TC33025VOETR |
7
TC33025
High Speed Double Ended Controller
TC33025-1 5/25/00
of the current–sense waveform, stability can be achieved
(see Figure 3).
One must be careful not to add too much ramp compen-
sation. If too much is added, the system will start to perform
like a voltage mode regulator. All benefits of current mode
control will be lost. Figures 11 and 12 show examples of two
different ways in which external ramp compensation can be
implemented.
A simple equation can be used to calculate the amount of
external ramp necessary to add that will achieve stability in the
current loop. For the following equations, the calculated
values for the application circuit in Figure 19 are also shown.
SE =
VOUT
(NS)(RS)AI
L
NP
where: VOUT = DC output voltage
NP, NS = number of power transformer primary
or secondary turns
AI = gain of the current sense network
(see Figures 8, 9 and 10)
L = output inductor
RS = current sense resistance
For the application circuit:
RSENSE =
1.0V
IPK (switch)
If the voltage at this pin exceeds 1.4V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the Soft–Start capacitor to be discharged. In
this way a “hiccup” mode of recovery is possible in the case
of output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
ISHUTDOWN =
1.4V
RSENSE
Undervoltage Lockout
There are two undervoltage lockout circuits within the
IC. The first senses VCC and the second VREF. During
power–up, VCC must exceed 9.2V and VREF must exceed
4.2V before the outputs can be enabled and the Soft–Start
latch released. If VCC falls below 8.4V or VREF falls below
3.6V, the outputs are disabled and the Soft–Start latch is
activated. When the UVLO is active, the part is in a low
current standby mode allowing the IC to have an off–line
bootstrap start–up circuit. Typical start–up current is 500
A.
Reference
A 5.1V bandgap reference is pinned out and is trimmed
to an initial accuracy of
±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA for
powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on wire–
wrap or plug–in prototype boards. With high frequency,
high power, switching power supplies it is imperative to have
separate current loops for the signal paths and for the power
paths. The printed circuit layout should contain a ground
plane with low current signal and high current switch and
output grounds returning on separate paths back to the input
filter capacitor. All bypass capacitors and snubbers should
be connected as close as possible to the specific part in
question. The PC board lead lengths must be less than 0.5
inches for effective bypassing or snubbing.
Instabilities
In current mode control, an instability can be encoun-
tered at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
If an external ramp (SE) is added to the on–time ramp (SN)
1.25V
Ramp Input
Ramp Compensation
SE
Current Signal
SN
+
SE =
5
(4 )(0.3)(0.55)
1.8
16
= 0.115V/
sec
Figure 3. Ramp Compensation
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