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參數(shù)資料
| 型號： | TC33025VOETR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 416K |
| 代理商： | TC33025VOETR |
TC33025
6
TC33025-1 5/25/00
High Speed Double Ended Controller
OPERATING DESCRIPTION
The TC33025 is a high speed, fixed frequency, double–
ended pulse width modulator controller optimized for high
frequency operation. They are specifically designed for
Off–Line and DC–to–DC converter applications offering the
designer a cost effective solution with minimal external
components. A representative block diagram is shown in
Figure 1.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. The RT pin
is set to a temperature compensated 3.0V. By selecting the
value of RT, the charge current is set through a current
mirror for the timing capacitor CT. This charge current runs
continuously through CT. The discharge current is ratioed to
be 10 times the charge current, which yields the maximum
duty cycle of 90%. CT is charged to 2.8V and discharged to
1.0V. During the discharge of CT, the oscillator generates
an internal blanking pulse that resets the PWM Latch,
inhibits the outputs, and toggles the steering flip–flop. The
threshold voltages on the oscillator comparator is trimmed
to guarantee an oscillator accuracy of 5.0% at 25
°C.
Additional dead time can be added by externally in-
creasing the charge current to CT as shown in Figure 6. This
changes the charge to discharge ratio of CT which is set
internally to ICHARGE/10 ICHARGE. The new charge to dis-
charge ratio will be:
% Deadtime =
IADDITIONAL + ICHARGE
10 (ICHARGE)
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of CT.
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge CT.
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 13 and 14 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95dB and a gain
bandwidth product of 8.3MHz with 75 degrees of phase
margin (Figure 24). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a Common Mode Voltage (VCM) input range of 1.5V to
5.5V. The Error Amplifier Output is provided for external
loop compensation.
Soft–Start Latch
Soft–Start is accomplished in conjunction with an exter-
nal capacitor. The soft start capacitor is charged by an
internal 9.0
A current source. This capacitor clamps the
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle.
The time it takes for a capacitor to reach full charge is
given by:
t
≈ (4.5 105) CSOFT-START
A Soft–Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft–Start circuit to latch so that the Soft–Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either VCC or VREF. The second
condition is when current sense input exceeds 1.4V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed, and the voltage at CSOFT–START is
less than 0.5V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25V offset such that whenever the
voltage at this pin exceeds the Error Amplifier Output volt-
age minus 1.25V, the PWM comparator will cause the PWM
latch to set, disabling the outputs. Once the PWM latch is set,
only a blanking pulse by the oscillator can reset it, thus
initiating the next cycle.
A toggle flip flop connected to the output of the PWM
latch controls which output is active. The flip flop is pulsed by
an OR gate that gets its inputs from the oscillator clock and
the output of the PWM latch. A pulse from either one will
cause the flip flop to enable the other output.
Current Limiting and Shutdown
A pin is provided to perform current limiting and shut-
down operations. Two comparators are connected to the
input of this pin. When the voltage at this pin exceeds 1.0V,
one of the comparators is activated. The output of this
comparator sets the PWM latch, which disables the output.
In this way cycle–by–cycle current limiting is accomplished.
If a current limit resistor is used in series with the power
devices, the value of the resistor is found by:
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