參數(shù)資料
型號(hào)： TB310
廠商： Intersil Corporation
英文描述： Decimating Digital Filter
中文描述： 元?dú)?，?shù)字濾波
文件頁數(shù)： 11/19頁
文件大?。?/td> 190K
代理商： TB310
3-204
There are two multiplexers that route 24 of the 40 output bits
from the output register to the output pins. The first
multiplexer selects the output register bits that will be routed
to output pins DATA_OUT16-23 and the second multiplexer
selects the output register bits that will be routed to output
pins DATA_OUT0-15.
The multiplexers are controlled by the control signal F_BYP
and the OUT_SELH pin. F_BYP and OUT_SELH both
control the first multiplexer that selects the upper 8 bits of
the output bus, DATA_OUT16-23. F_BYP controls the
second multiplexer that selects the lower 16 bits of the
output bus, DATA_OUT0-15. The output formatter is shown
in detail in Figure 10.
FIR Control Logic
The DATA_RDY strobe indicates that new data is available on
the output of the FIR. The rising edge of DATA_RDY can be
used to load the output data into an external register or RAM.
Data Format
The DDF maintains 16 bits of accuracy in both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.
FIGURE 9. FIR FILTER
REG
REG
REG
REG
REG
PRE-ADDER
16
F_ESYM
F_OAD
16
17
16
16
17
PRE-ADDER LOGIC
20
20
17
17 x 20 BIT MULTIPLIER ARRAY
REG
43-BIT ACCUMULATOR
37
37
43
43
F_CLA
MULTIPLIER/
ACCUMULATOR
SECTION
FROM HDF
FROM COEFFICIENT
FORMATTER
16
20
16 x 512
DATA
RAM
20 x 256
COEFFICIENT
RAM
OUTPUT
FORMATTER
OUTPUT REG
MUX
40
F_CLA
DATA_RDY
FIR_CK
DATA_OUT 0 -23
REG
FIR_CK
DATA_RDY
FROM CONTROL REGISTERS
F_DRATE
F_TAPS
F_BYP
F_DIS
FIR CONTROL LOGIC
24
FIGURE 10. FIR OUTPUT FORMATTER
OUT_SELH
16
DATA_OUT0 -15
16 16
F_BYP
OUT_ENP
F_BYP = 1
2
-16
- 2
-31
F_BYP = 0
40
MUX
2
0
- 2
-15
8
DATA_OUT16-23
8
8
F_BYP
OUT_ENX
F_BYP = 0
OUT_SELH = 1
2
8
- 2
1
F_BYP = 0
OUT_SELH = 0
OR
F_BYP = 1
MUX
2
-16
- 2
-23
HSP43220
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